FEATURES
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High Performance Stereo Audio ADC
APPLICATIONS
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Soundbar
Audio Interface
Digital TV
A/V Receiver
DVR
NVR
ES7240S
High performance multi-bit delta-sigma
audio ADC
100 dB signal to noise ratio
-85 dB THD+N
24-bit, 8 to 200 kHz sampling frequency
I
2
S/LJ master or slave serial data port
256/384Fs and other non standard
audio system clocks
Low power standby mode
ORDERING INFORMATION
ES7240S -40°C ~ +85°C
TSSOP-16
BLOCK DIAGRAM
AINL
AINR
Multi-bit
Delta-sigma
Modulator
DSP
Audio
Data
Interface
SDOUT
SCLK
LRCK
Clock Manager
Sample Rate Detector
Control
Interface
MCLK
M1 M0
1
Everest Semiconductor
Confidential
ES7240S
1.
2.
3.
4.
5.
6.
PIN OUT AND DESCRIPTION ................................................................................................ 3
TYPICAL APPLICATION CIRCUIT.......................................................................................... 4
CLOCK MODES AND SAMPLING FREQUENCIES ............................................................... 5
POWER UP AND POWER DOWN .......................................................................................... 5
DIGITAL AUDIO INTERFACE.................................................................................................. 5
ELECTRICAL CHARACTERISTICS ....................................................................................... 6
ABSOLUTE MAXIMUM RATINGS.................................................................................................. 6
RECOMMENDED OPERATING CONDITIONS ................................................................................ 6
ADC ANALOG AND FILTER CHARACTERISTICS AND SPECIFICATIONS .......................................... 6
POWER CONSUMPTION CHARACTERISTICS ................................................................................ 7
SERIAL AUDIO PORT SWITCHING SPECIFICATIONS ..................................................................... 7
7.
8.
PACKAGE ................................................................................................................................ 9
CORPORATE INFORMATION .............................................................................................. 10
Revision 8.0
2
September 2018
Latest datasheet:
www.everest-semi.com
or
info@everest-semi.com
Everest Semiconductor
Confidential
ES7240S
1. PIN OUT AND DESCRIPTION
M0
MCLK
VDDP
SDOUT
GNDD
VDDD
SCLK
LRCK
1
2
3
4
5
6
7
8
ES7240S
16
15
14
13
12
11
10
9
M1
REFP
GNDA
VDDA
AINR
REFQ
AINL
RESETb
Pin Name
M0, M1
MCLK
SCLK
LRCK
SDOUT
RESETb
AINL, AINR
VDDP
VDDD/GNDD
VDDA/GNDA
REFP
REFQ
Pin number
1, 16
2
7
8
4
9
10,12
3
6, 5
13, 14
15
11
Input or Output
I
I
I/O
I/O
O
I
I
I
I
I
O
O
Pin Description
Mode selection
Master clock
Serial data bit clock
Serial data left and right channel frame clock
Serial data output
Active low chip reset (low power)
Analog left and right inputs
Power supply for the digital input and output
Digital power supply
Analog power supply
Filtering capacitor connection
Filtering capacitor connection
Revision 8.0
3
September 2018
Latest datasheet:
www.everest-semi.com
or
info@everest-semi.com
Everest Semiconductor
Confidential
ES7240S
2. TYPICAL APPLICATION CIRCUIT
For the best performance,decoupling and filtering capacitors should be located as close to the device package as possible
Additional parallel capacitors(typically 0.1 μF) can be used, larger value capacitors(typically 10 μF) would also help
*
AGND AGND
*
100nF
PV
DD(+3V
3)
DVDD(+3V3)
AGND
*
100nF
3
6
5
9
1
16
2
7
8
4
10K
PV
DD(+3V
3)
ES7240S
V
DDP
V
DDD
GNDD
RESETb
M0
M1
MCL
K
SCLK
LRCK
SDOUT
Everest
V
DDA
13
1uF
AVDD(+3V3)
GNDA
REFP
REFQ
AINR
AINL
14
15
11
1uF
12
10
1uF
RIN
LIN
*
**
1uF
AGND
1uF
CPU/DSP
GND(SYS)
These formats are I2S (pull up resistor at SDOUT pin)
and left justified (pull down resistor at SDOUT pin)
0R
AGND
In the layout, chip is treated as an analog device
Revision 8.0
4
September 2018
Latest datasheet:
www.everest-semi.com
or
info@everest-semi.com
Everest Semiconductor
Confidential
ES7240S
3. CLOCK MODES AND SAMPLING FREQUENCIES
The device can work either in master clock mode or slave clock mode by setting mode control
pins M1 and M0 according to Table 1.
Table 1 Mode Control
Pin
M1:M0
Pin Description
00 – master clock mode, single speed mode
01 – master clock mode, double speed mode
10 – master clock mode, quad speed mode
11 – slave clock mode, all speed modes
In master mode, LRCK and SCLK are derived internally from MCLK. The available MCLK/LRCK
ratios are listed in Table 2. SCLK/LRCK ratio is always 64 in master mode.
Table 2 Master Mode Sampling Frequencies and MCLK/LRCK Ratio
Speed Mode
Single Speed
Double Speed
Quad Speed
Sampling Frequency
8kHz – 50kHz
50kHz – 100kHz
100kHz – 200kHz
MCLK/LRCK Ratio
256
128
64
In slave mode, LRCK and SCLK are supplied externally. LRCK and SCLK must be synchronously
derived from the system clock with some specific rates. The device can auto detect MCLK/LRCK
ratio according to Table 3. The device only supports the MCLK/LRCK ratios listed in Table 3. The
SCLK/LRCK ratio is normally 64.
Table 3 Slave Mode Sampling Frequencies and MCLK/LRCK Ratio
Speed Mode
Single Speed
Double Speed
Quad Speed
Sampling Frequency
8kHz – 50kHz
50kHz – 100kHz
100kHz – 200kHz
MCLK/LRCK Ratio
256, 384, 512, 768, 1024
128, 192
64
4. POWER UP AND POWER DOWN
RESETb pin active low will put the device in power down mode. During power-up, RESETb pin
should be hold at low level to keep the device in reset until the power supplies, clocks and mode
selection pins are stable.
5. DIGITAL AUDIO INTERFACE
The device provides many formats of serial audio data interface to the output from the ADC
through LRCK, SCLK and SDOUT pins. These formats are I
2
S (pull up resistor at SDOUT pin) and
left justified (pull down resistor at SDOUT pin). ADC data is out at SDOUT on the falling edge of
Revision 8.0
5
September 2018
Latest datasheet:
www.everest-semi.com
or
info@everest-semi.com