ES7144LV
10-pin, 24-Bit, 192 kHz Stereo D/A Converter for PCM Audio
GENERAL DESCRIPTION
The ES7144LV is a low cost 10-pin
stereo digital to analog converter. The
ES7144LV can accept I²S serial audio
data format up to 24-bit word length.
The device uses advanced multi-bit
∆-∑
modulation technique to convert data
into two channel analog outputs. The
multi-bit
∆
-∑ modulator makes the
device with very low sensitivity to clock
jitter and very low out of band noise.
FEATURES
100 dB SNR
-85 dB THD+N
Up to 200 kHz sampling frequency
I
2
S audio data format, 16-24 bits
Single power supply 3V to 5.5V
APPLICATIONS
Digital Photo Frame
Set top box
Digital TV
DVD player
Audio player
ORDERING INFORMATION
ES7144LV -40°C ~ +85°C
TSSOP-10 (Same as MSOP-10)
BLOCK DIAGRAM
SDATA
SCLK
LRCK
Audio
Data
Interface
Interpolation
Filter
Multi-level
Sigma-delta
DAC
Output Amp
Low Pass
Filter
AOUTL
Clock Manager/
Sample Rate
Detector
Interpolation
Filter
Multi-level
Sigma-delta
DAC
Output Amp
Low Pass
Filter
AOUTR
CLKIN
Rev 7.0
1
May, 2017
Everest Semiconductor
1. PIN DESCRIPTIONS
ES7144LV
SDATA
SCLK
LRCK
CLKIN
CAP1
PIN
1
2
3
4
5
6
7
8
9
10
PIN
SDATA
SCLK
LRCK
CLKIN
CAP1
CAP2
AOUTL
GND
VDD
AOUTR
I/O
I
I
I
I
O
O
O
I
I
O
1
2
3
4
5
DESCRIPTION
Serial audio data input
Bit clock input
ES7144LV
10
9
8
7
6
AOUTR
VDD
GND
AOUTL
CAP2
Left and right channel clock input indicating input data sampling
rate (Fs) and channel selection
System clock input
Filtering capacitor
Filtering capacitor
Analog output of left channel
Ground
Device power supply
Analog output of right channel
2. RECOMMENDED APPLICATION CIRCUIT
Figure 1 Recommended Application Circuit
Rev 7.0
2
May, 2017
Everest Semiconductor
3. APPLICATION DESCRIPTIONS
Sampling Rate and Input Clocks
ES7144LV
The serial audio input data is transmitted to the device at SDATA pin. According to the
sampling rate, the device can work in three speed modes, single speed, double
speed and quad speed. The device can detect the speed mode of the input data
stream automatically when the sampling rate falls into the auto detection ranges
listed in Table1. If the sampling rate is outside the auto detection ranges, the device
will not work properly.
Table 1 Auto Detection Ranges and CLKIN/LRCK Ratio
MODE
Single Speed
Double Speed
Quad Speed
Fs Auto Detection Range
8kHz – 50kHz
84kHz – 100kHz
167kHz – 200kHz
CLKIN/LRCK Ratio
256, 384, 512, 768, 1024
128, 192, 256, 384, 512
128, 192, 256
The device works with the input system clock CLKIN, sample data clock LRCK and
bit clock SCLK. The data clock and bit clock must be synchronously derived from the
system clock with some specific rates. The device only supports the CLKIN/LRCK
ratios listed in Table1. The LRCK/SCLK ratio is normally 64. The device detects clock
ratios automatically, and it will not work properly if any ratio is incorrect.
Audio Data Input
The ES7144LV can accept I²S serial audio input data from 16-bit to 24-bit. The
device can detect the data word length automatically. The relationship of SDATA,
SCLK and LRCK for the format is illustrated through Figures 2.
1 SCLK
SDATA
1
MSB
SCLK
LEFT CHANNEL
2
3
n-2 n-1
n
LSB
1 SCLK
1
MSB
2
3
n-2 n-1
n
LSB
LRCK
RIGHT CHANNEL
Figure 2 I²S serial audio data format up to 24-bit
Power Up and Power Down
The device resets itself when VDD ramp from ground voltage to supply voltage. The
ground voltage needs to be less than 0.2V for proper reset. When VDD voltage is
removed, it is important to let it drop below 0.2V before next power up. An optional
discharge resistor (3.3K, for example) can be placed between VDD and GND.
Rev 7.0
3
May, 2017
Everest Semiconductor
ES7144LV
Upon applying VDD, the device will reset itself and enter power down state. During
this state, the device clamps outputs to ground and power down the device operation
except for clock management unit. Once proper CLKIN and LRCK clocks are applied,
the device will leave power down state, and the device outputs ramp from ground to
common mode voltage softly. Then the device enters the normal operation
.
4. ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
At or beyond this condition, operating continuously may cause permanent damage to
the device. The performance and functions of the device are not guaranteed at these
extremes.
PARAMETER
Supply Voltage Level
Input Voltage Range
Operating Temperature Range
Storage Temperature
MIN
-0.3V
GND-0.3V
-40°C
-65°C
MAX
+7.0V
VDD+0.3V
+85°C
+150°C
Recommended Operating Conditions
PARAMETER
Supply Voltage Level
MIN
3
TYP
3.3
MAX
5.5
UNIT
V
Analog Characteristics
Test conditions: VDD=3.3V, GND=0V, ambient temperature=25°C, Fs=48KHz,
CLKIN/LRCK=256, input 0dB 1KHz sinewave
PARAMETER
DAC Performance
Signal to Noise Ratio (Note 1)
THD+N
Channel Separation (1KHz)
Dynamic Range
Interchannel Gain Mismatch
Frequency Response
(20Hz-20KHz)
Filter Frequency Response characteristics
Single Speed
Passband
Stopband
Passband Ripple
Rev 7.0
4
0
0.547
±0.05
0.454
Fs
Fs
dB
May, 2017
-0.02
90
100
-85
100
100
0
+0.08
-80
dB
dB
dB
dB
dB
dB
MIN
TYP
MAX
UNIT
Everest Semiconductor
Stopband Attenuation
Double Speed
Passband
Stopband
Passband Ripple
Stopband Attenuation
Quad Speed
Passband
Stopband
Passband Ripple
Stopband Attenuation
Analog Output Characteristics
Full Scale Output Level
Output Impedance
Minimum Load Resistance
Maximum Capacitance
0.7*VDD
120
2
100
-50
0
0.792
±0.006
0.2083
Fs
Fs
dB
dB
-56
0
0.583
±0.005
0.417
Fs
Fs
dB
dB
-53
dB
ES7144LV
Vpp
Ω
KΩ
pF
Note 1. A-weighted filter is used in measurement.
Rev 7.0
5
May, 2017
微控制器 MCU
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