ES7243
High Performance Stereo Audio ADC
FEATURES
High performance multi-bit delta-sigma
audio ADC
102 dB signal to noise ratio
-95 dB THD+N
24-bit, 8 to 200 kHz sampling frequency
I
2
S/PCM master or slave serial data port
Support TDM
256/384Fs, USB 12/24 MHz and other
non standard audio system clocks
Low power standby mode
APPLICATIONS
Mic Array
Soundbar
Audio Interface
Digital TV
A/V Receiver
DVR
NVR
ORDERING INFORMATION
ES7243 -40°C ~ +85°C
QFN-20
BLOCK DIAGRAM
TDMIN
AINLP/AINLN
AINRP/AINRN
Multi-bit
Delta-sigma
Modulator
DSP
Audio
Data
Interface
SDOUT
SCLK
LRCK
Clock Manager
Sample Rate Detector
IC
Interface
2
MCLK
CCLK CDATA AD0 AD1
1
Everest Semiconductor
Confidential
ES7243
3. CLOCK MODES AND SAMPLING FREQUENCIES
The device supports standard audio clocks (256Fs, 384Fs, 512Fs, etc), USB clocks (12/24 MHz),
and some common non standard audio clocks (25 MHz, 26 MHz, etc).
According to the serial audio data sampling frequency (Fs), the device can work in two speed
modes: single speed mode or double speed mode. In single speed mode, Fs normally ranges
from 8 kHz to 48 kHz, and in double speed mode, Fs normally range from 64 kHz to 96 kHz.
The device can work either in master clock mode or slave clock mode. In slave mode, LRCK and
SCLK are supplied externally, and LRCK and SCLK must be synchronously derived from the
system clock with specific rates. In master mode, LRCK and SCLK are derived internally from
device master clock.
4. MICRO-CONTROLLER CONFIGURATION INTERFACE
The device supports standard I
2
C micro-controller configuration interface. External micro-
controller can completely configure the device through writing to internal configuration
registers.
I
2
C interface is a bi-directional serial bus that uses a serial data line (CDATA) and a serial clock
line (CCLK) for data transfer. The timing diagram for data transfer of this interface is given in
Figure 1a and Figure 1b. Data are transmitted synchronously to CCLK clock on the CDATA line on
a byte-by-byte basis. Each bit in a byte is sampled during CCLK high with MSB bit being
transmitted firstly. Each transferred byte is followed by an acknowledge bit from receiver to pull
the CDATA low. The transfer rate of this interface can be up to 400 kbps.
A master controller initiates the transmission by sending a “start” signal, which is defined as a
high-to-low transition at CDATA while CCLK is high. The first byte transferred is the slave address.
It is a seven-bit chip address followed by a RW bit. The chip address must be 0010 0x, where x
equals A
AD0. The RW bit indicates the slave data transfer direction. Once an acknowledge
bit is received, the data transfer starts to proceed on a byte-by-byte basis in the direction
specified by the RW bit. The master can terminate the communication by generating a “stop”
signal, which is defined as a low-to-high transition at CDATA while CCLK is high.
In I
2
C interface mode, the registers can be written and read. The formats of “write” and “read”
instructions are shown in Table 1 and Table 2. Please note that, to read data from a register, you
must set R/W bit to 0 to access the register address and then set R/W to 1 to read data from the
register.
Table 1 Write Data to Register in I
2
C Interface Mode
Chip Address
A
AD0
R/W
0
Register Address
RAM
Data to be written
DATA
start
ACK
ACK
ACK
Stop
Revision 8.1
4
January 2019
Latest datasheet:
www.everest-semi.com
or
info@everest-semi.com
Everest Semiconductor
Confidential
ES7243
Chip Addr
Write ACK
Reg Addr
ACK
Write Data
ACK
CDATA
CCLK
bit 1 to 7
bit 1 to 8
bit 1 to 8
START
STOP
Figure 1a I
2
C Write Timing
Table 2 Read Data from Register in I
2
C Interface Mode
Chip Address
A
AD0
Chip Address
A
AD0
Chip Addr
Write ACK
Start
Start
R/W
0
R/W
1
Reg Addr
ACK
ACK
ACK
Register Address
RAM
Data to be read
Data
Chip Addr
Read ACK
ACK
NACK
Stop
Read Data NO ACK
CDATA
CCLK
bit 1 to 7
bit 1 to 8
bit 1 to 7
bit 1 to 8
START
START
STOP
Figure 1b I
2
C Read Timing
5. DIGITAL AUDIO INTERFACE
The device provides many formats of serial audio data interface to the output from the ADC
through LRCK, SCLK and SDOUT pins. These formats are I
2
S, left justified and DSP/PCM mode.
ADC data is out at SDOUT on the falling edge of SCLK. The relationships of SDOUT (SDATA), SCLK
and LRCK with these formats are shown through Figure 2 to Figure 5. The device supports up to
8-ch of TDM, please refer to user guide for detail description.
1 SCLK
SDATA
1
MSB
SCLK
LEFT CHANNEL
2
3
n-2 n-1
n
LSB
1 SCLK
1
MSB
2
3
n-2 n-1
n
LSB
LRCK
RIGHT CHANNEL
Figure 2 I
2
S Serial Audio Data Format Up To 24-bit
Revision 8.1
5
January 2019
Latest datasheet:
www.everest-semi.com
or
info@everest-semi.com
微控制器 MCU
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