In the lay o ut, c h ip is treated as an an alo g d ev ice
33
6
7
VD DM
0R
1uF 1uF 1uF 1uF 1uF
29
30
25
18
17
21
23
22
GND (SY S)
* * * * *
RE FQ M
RE FQ 1 2
RE FP1 2
G N DA
*
*
AGND
1uF
26
28
27
31
32
AGND
1uF
VD DA
1uF
AGND
RE FP3 4
RE FQ 3 4
V D DM
V D DA
VD DP
VD DC
AGND
100nF
PGND
* *
AGND
VD DP
VD DD
*
M icbias34
1uF
1uF
1uF
1uF
M ic4P
M ic4N
M ic3P
M ic3N
M ICBIAS34
M IC4P
M IC4N
M IC3P
M IC3N
100nF
8
1
2
3
4
5
9
10
11
12
GNDD
AD0
AD1
CD ATA
CCLK
M CLK
SCLK
LRCK
SDOUT 1/TDM O UT
SDOUT 2/TDM IN
INT
DM IC_CLK
ES7210
Everes t
IIC
*
M icbias12
1uF
1uF
1uF
1uF
M ic2P
M ic2N
M ic1P
M ic1N
IIS
GPIO
100K
M ICBIAS12
M IC2P
M IC2N
M IC1P
M IC1N
24
19
20
16
15
VD DP
13
14
Fo r th e b es t pe rfo rm an ce ,d ec o up lin g an d f ilterin g c ap ac ito r s s h o u ld b e loc ated as c lo s e to th e d evice p ac kag e as po s s ib le
Ad d itio n al par allel ca pac ito rs (ty p ically 0 .1 μF ) c an b e us ed , larg er v alu e c ap ac ito r s (typ ic ally 1 0 μF ) w o u ld als o help
*
3. CLOCK MODES AND SAMPLING FREQUENCIES
The device supports standard audio clocks (256Fs, 384Fs, 512Fs, etc), USB clocks (12/24 MHz),
and some common non standard audio clocks (25 MHz, 26 MHz, etc).
According to the serial audio data sampling frequency (Fs), the device can work in two speed
modes: single speed mode or double speed mode. In single speed mode, Fs normally ranges
from 8 kHz to 48 kHz, and in double speed mode, Fs normally range from 64 kHz to 96 kHz.
The device can work either in master clock mode or slave clock mode. In slave mode, LRCK and
SCLK are supplied externally, and LRCK and SCLK must be synchronously derived from the
system clock with specific rates. In master mode, LRCK and SCLK are derived internally from
device master clock.
4. MICRO-CONTROLLER CONFIGURATION INTERFACE
The device supports standard I
2
C micro-controller configuration interface. External micro-
controller can completely configure the device through writing to internal configuration
registers.
I
2
C interface is a bi-directional serial bus that uses a serial data line (CDATA) and a serial clock
line (CCLK) for data transfer. The timing diagram for data transfer of this interface is given in
Figure 1a and Figure 1b. Data are transmitted synchronously to CCLK clock on the CDATA line on
a byte-by-byte basis. Each bit in a byte is sampled during CCLK high with MSB bit being
transmitted firstly. Each transferred byte is followed by an acknowledge bit from receiver to pull
the CDATA low. The transfer rate of this interface can be up to 400 kbps.
Revision 9.1
3
January 2019
Latest datasheet:
www.everest-semi.com
or
info@everest-semi.com
Everest Semiconductor
Confidential
ES7210
A master controller initiates the transmission by sending a “start” signal, which is defined as a
high-to-low transition at CDATA while CCLK is high. The first byte transferred is the slave address.
It is a seven-bit chip address followed by a RW bit. The chip address must be 1000 0x, where x
equals AD1 AD0. The RW bit indicates the slave data transfer direction. Once an acknowledge bit
is received, the data transfer starts to proceed on a byte-by-byte basis in the direction specified
by the RW bit. The master can terminate the communication by generating a “stop” signal,
which is defined as a low-to-high transition at CDATA while CCLK is high.
In I
2
C interface mode, the registers can be written and read. The formats of “write” and “read”
instructions are shown in Table 1 and Table 2. Please note that, to read data from a register, you
must set R/W bit to 0 to access the register address and then set R/W to 1 to read data from the
register.
Table 1 Write Data to Register in I
2
C Interface Mode
Chip Address
1000 0 AD1 AD0
R/W
0
Register Address
RAM
Data to be written
DATA
start
ACK
ACK
ACK
Stop
Chip Addr
Write ACK
Reg Addr
ACK
Write Data
ACK
CDATA
CCLK
bit 1 to 7
bit 1 to 8
bit 1 to 8
START
STOP
Figure 1a I
2
C Write Timing
Table 2 Read Data from Register in I
2
C Interface Mode
Chip Address
1000 0 AD1 AD0
Chip Address
1000 0 AD1 AD0
Chip Addr
Write ACK
Start
Start
R/W
0
R/W
1
Reg Addr
ACK
ACK
ACK
Register Address
RAM
Data to be read
Data
Chip Addr
Read ACK
ACK
NACK
Stop
Read Data NO ACK
CDATA
CCLK
bit 1 to 7
bit 1 to 8
bit 1 to 7
bit 1 to 8
START
START
STOP
Figure 1b I
2
C Read Timing
Revision 9.1
4
January 2019
Latest datasheet:
www.everest-semi.com
or
info@everest-semi.com
Everest Semiconductor
Confidential
ES7210
5. DIGITAL AUDIO INTERFACE
The device provides many formats of serial audio data interface to the output from the ADC
through LRCK, SCLK and SDOUT pins. These formats are I
2
S, left justified, DSP/PCM mode and
TDM. ADC data is out at SDOUT on the falling edge of SCLK. The relationships of SDOUT, SCLK
and LRCK with these formats are shown through Figure 2a to Figure 2h. ES7210 can be cascaded
up to 16-ch through single I
2
S or TDM, please refer to the user guide for detail description.
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