ES7144S
10-pin, 24-Bit Stereo D/A Converter for PCM Audio
GENERAL DESCRIPTION
The ES7144S is a low cost 10-pin
stereo digital to analog converter. The
ES7144S can accept I²S serial audio
data format up to 24-bit word length.
The device uses advanced multi-bit
∆-∑
modulation technique to convert data
into two channel analog outputs. The
multi-bit
∆
-∑ modulator makes the
device with very low sensitivity to clock
jitter and very low out of band noise.
FEATURES
100 dB SNR
-85 dB THD+N
Up to 100 kHz sampling frequency
Support USB clocks or non standard
audio clocks like 25 MHz or 26 MHz
I
2
S audio data format, 16-24 bits
Single power supply 3V to 3.6V
APPLICATIONS
Digital Photo Frame
Set top box
Digital TV
DVD player
Audio player
ORDERING INFORMATION
ES7144S
-40°C ~ +85°C
TSSOP-10 (Same as MSOP-10)
BLOCK DIAGRAM
SDATA
SCLK
LRCK
Audio
Data
Interface
Interpolation
Filter
Multi-level
Sigma-delta
DAC
Output Amp
Low Pass
Filter
AOUTL
Clock Manager/
Sample Rate
Detector
Interpolation
Filter
Multi-level
Sigma-delta
DAC
Output Amp
Low Pass
Filter
AOUTR
CLKIN
Rev 3.0
September 2018
1
Latest datasheet:
http://www.everest-semi.com
or
info@everest-semi.com
Everest Semiconductor
1. PIN DESCRIPTIONS
ES7144S
SDATA
SCLK
LRCK
CLKIN
CAP1
PIN
1
2
3
4
5
6
7
8
9
10
PIN
SDATA
SCLK
LRCK
CLKIN
CAP1
CAP2
AOUTL
GND
VDD
AOUTR
I/O
I
I
I
I
O
O
O
I
I
O
1
2
3
4
5
DESCRIPTION
Serial audio data input
Bit clock input
ES7144S
10
9
8
7
6
AOUTR
VDD
GND
AOUTL
CAP2
Left and right channel clock input indicating input data sampling
rate (Fs) and channel selection
System clock input
Filtering capacitor
Filtering capacitor
Analog output of left channel
Ground
Device power supply
Analog output of right channel
2. RECOMMENDED APPLICATION CIRCUIT
AGND
AGND
GND(SYS)
0R
In the layout, chip is treated as an analog device
ES7144S
1
2
SDATA
SCLK
LRCK
CLKIN
CAP1
AOUTR
V
DD
GND
AOUTL
CAP2
10
9
8
7
6
3.3uF
470R
2200pF
AOUTL
CPU/DSP
3
4
*
*
V
DD
1uF
3.3uF
AGND
AGND
AGND
470R
2200pF
AOUTR
*
5
1uF
AGND
1uF
For the best performance,decoupling and filtering capacitors should be located as close to the device package as possible
Additional parallel capacitors(typically 0.1 μF) can be used, larger value capacitors(typically 10 μF) would also help
*
Figure 1 Recommended Application Circuit
Rev 3.0
September 2018
2
Latest datasheet:
http://www.everest-semi.com
or
info@everest-semi.com
Everest Semiconductor
3. APPLICATION DESCRIPTIONS
Sampling Rate and Input Clocks
ES7144S
According to the sampling rate, the device can work in two speed modes, single
speed and double speed. Table 1 lists the typical clock modes supported by the
device. The device supports USB clocks or non standard audio clocks like 25 MHz or
26 MHz.
Table 1 Speed Mode and CLKIN/LRCK Ratio
MODE
Single Speed
Double Speed
Sampling Rate
8kHz – 50kHz
84kHz – 100kHz
CLKIN/LRCK Ratio
32, 64, 128, 192, 256, 384, 512, 768, 1024
128, 192, 256, 384, 512, 768, 1024
Audio Data Input
The ES7144S can accept I²S serial audio input data from 16-bit to 24-bit. The device
can detect the data word length automatically. The relationship of SDATA, SCLK and
LRCK for the format is illustrated through Figures 2.
1 SCLK
SDATA
1
MSB
SCLK
LEFT CHANNEL
2
3
n-2 n-1
n
LSB
1 SCLK
1
MSB
2
3
n-2 n-1
n
LSB
LRCK
RIGHT CHANNEL
Figure 2 I²S serial audio data format up to 24-bit
Power Up and Power Down
Upon applying VDD, the device will reset itself and enter power down state. During
this state, the device clamps outputs to ground and power down the device operation
except for clock management unit. Once proper CLKIN and LRCK clocks are applied,
the device will leave power down state, and the device outputs ramp from ground to
common mode voltage softly. Then the device enters the normal operation
.
Rev 3.0
September 2018
3
Latest datasheet:
http://www.everest-semi.com
or
info@everest-semi.com
Everest Semiconductor
4. ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
ES7144S
At or beyond this condition, operating continuously may cause permanent damage to
the device. The performance and functions of the device are not guaranteed at these
extremes.
PARAMETER
Supply Voltage Level
Input Voltage Range
Operating Temperature Range
Storage Temperature
MIN
-0.3V
GND-0.3V
-40°C
-65°C
MAX
+5.0V
VDD+0.3V
+85°C
+150°C
Recommended Operating Conditions
PARAMETER
Supply Voltage Level
MIN
3
TYP
3.3
MAX
3.6
UNIT
V
Analog Characteristics
Test conditions: VDD=3.3V, GND=0V, ambient temperature=25°C, Fs=48KHz,
CLKIN/LRCK=256, input 0dB 1KHz sinewave
PARAMETER
DAC Performance
Signal to Noise Ratio (Note 1)
THD+N
Channel Separation (1KHz)
Dynamic Range
Interchannel Gain Mismatch
Frequency Response
(20Hz-20KHz)
Filter Frequency Response characteristics
Single Speed
Passband
Stopband
Passband Ripple
Stopband Attenuation
Double Speed
Passband
Stopband
Passband Ripple
Rev 3.0
0
0.583
±0.005
0.417
Fs
Fs
dB
-53
0
0.547
±0.05
0.454
Fs
Fs
dB
dB
-0.02
90
100
-85
100
102
0
+0.08
-80
dB
dB
dB
dB
dB
dB
MIN
TYP
MAX
UNIT
September 2018
4
Latest datasheet:
http://www.everest-semi.com
or
info@everest-semi.com
Everest Semiconductor
Stopband Attenuation
Quad Speed
Passband
Stopband
Passband Ripple
Stopband Attenuation
Analog Output Characteristics
Full Scale Output Level
Output Impedance
Minimum Load Resistance
Maximum Capacitance
0.7*VDD
120
2
100
-50
0
0.792
±0.006
0.2083
Fs
Fs
dB
dB
-56
dB
ES7144S
Vpp
Ω
KΩ
pF
Note 1. A-weighted filter is used in measurement.
Rev 3.0
September 2018
5
Latest datasheet:
http://www.everest-semi.com
or
info@everest-semi.com
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