FEATURES
System
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Low Power Audio CODEC
DAC
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ES8316
High performance and low power multi-
bit delta-sigma audio ADC and DAC
I
2
S/PCM master or slave serial data port
Two pairs of analog input with
differential input option
256/384Fs and USB 12/24 MHz system
clocks
Sophisticated analog input and output
routing, mixing and gain
I
2
C interface
24-bit, 8 to 96 kHz sampling frequency
93 dB signal to noise ratio, -85 dB
THD+N
Ground centered headphone driver
3-band PEQ
Stereo enhancement
Headphone and external mic detection
Pop and click noise suppression
Low Power
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1.8V to 3.3V operation
7 mW playback; 16 mW playback and
record
ADC
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24-bit, 8 to 96 kHz sampling frequency
92 dB signal to noise ratio, -85 dB
THD+N
Low noise pre-amplifier
Auto level control (ALC) and noise gate
Mic bias
Support digital mic
APPLICATIONS
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MID/Tablet
Wireless audio
Portable audio
ORDERING INFORMATION
ES8316 -40°C ~ +85°C
QFN-32
1
Everest Semiconductor
Confidential
ES8316
3. TYPICAL APPLICATION CIRCUIT
AGND
GND(SYS)
0R
AGND
MICBIAS
In the layout, chip is treated as an analog device
1uF
AVDD
CPVDD-1V8
23
17
26
22
14
*
* *
1uF
1uF
AGND AGND
LIN1
RIN1
LIN2
30
1uF
29
1uF
28
1uF
27
20
19
33R
33R
1uF
5
4
Mic1P
Mic1N
Mic2P
Mic2N
LOUT
ROUT
GND
PV
DD
MIC
HP_CTIA
GNDA
CPGND
VDDA
12
GPIO3
CCLK
CDATA
CE0
MCL
K
SCLK
LRCK
DSIN
ADSOUT
PV
DD
DVDD
CPU/DSP
1
32
31
2
6
8
7
9
4
3
Everest
ES8316
MICBIAS
CPVDD
RIN2
HPL
HPR
VMID
CPN
0.1uF
0.1uF
AGND
AGND AGND
CPP
DGND
PGND
CPVSSP
**
5
33
DACVREF
ADCVREF
PV
DD
DVDD
CPGNDREF
GPIO1
GPIO2
3
6
AGND
2
18
10
HP-INSET
7
10K
11
HP-MIC
1
8
16
15
24
13
****
1uF
1uF 1uF 1uF 1uF
AGND
For the best performance,decoupling and filtering capacitors should be located as close to the device package as possible
Additional parallel capacitors(typically 0.1 μF) can be used, larger value capacitors(typically 10 μF) would also help
*
Revision 6.0
4
September 2018
Latest datasheet:
www.everest-semi.com
or
info@everest-semi.com
21
25
Pin18 must be connected to the AGND junction on HP
Everest Semiconductor
Confidential
ES8316
4. CLOCK MODES AND SAMPLING FREQUENCIES
The device supports two types of clocking: standard audio clocks (256Fs, 384Fs, 512Fs, etc), and
USB clocks (12/24 MHz).
According to the serial audio data sampling frequency (Fs), the device can work in two speed
modes: single speed mode or double speed mode. In single speed mode, Fs normally ranges
from 8 kHz to 48 kHz, and in double speed mode, Fs normally range from 64 kHz to 96 kHz.
The device can work either in master clock mode or slave clock mode. In slave mode, LRCK and
SCLK are supplied externally, and LRCK and SCLK must be synchronously derived from the
system clock with specific rates. In master mode, LRCK and SCLK are derived internally from
device master clock.
5. MICRO-CONTROLLER CONFIGURATION INTERFACE
The device supports standard I
2
C micro-controller configuration interface. External micro-
controller can completely configure the device through writing to internal configuration
registers.
I
2
C interface is a bi-directional serial bus that uses a serial data line (SDA) and a serial clock line
(SCL) for data transfer. The timing diagram for data transfer of this interface is given in Figure 1.
Data are transmitted synchronously to SCL clock on the SDA line on a byte-by-byte basis. Each
bit in a byte is sampled during SCL high with MSB bit being transmitted firstly. Each transferred
byte is followed by an acknowledge bit from receiver to pull the SDA low. The transfer rate of
this interface can be up to 400 kbps.
Figure 1 Data Transfer for I
2
C Interface
A master controller initiates the transmission by sending a “start” signal, which is defined as a
high-to-low transition at SDA while SCL is high. The first byte transferred is the slave address. It
is a seven-bit chip address followed by a RW bit. The chip address must be 001000x, where x
equals AD0. The RW bit indicates the slave data transfer direction. Once an acknowledge bit is
received, the data transfer starts to proceed on a byte-by-byte basis in the direction specified by
the RW bit. The master can terminate the communication by generating a “stop” signal, which is
defined as a low-to-high transition at SDA while SCL is high.
Revision 6.0
5
September 2018
Latest datasheet:
www.everest-semi.com
or
info@everest-semi.com
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