FEATURES
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High Performance Stereo Audio ADC
APPLICATIONS
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Soundbar
Audio Interface
Digital TV
A/V Receiver
DVR
NVR
ES7241D
High performance multi-bit delta-sigma
audio ADC
100 dB signal to noise ratio
-85 dB THD+N
3 Vpp analog input
24-bit, 8 to 200 kHz sampling frequency
I
2
S/LJ master or slave serial data port
256/384Fs and other non standard
audio system clocks
Low power standby mode
ORDERING INFORMATION
ES7241D -40°C ~ +85°C
QFN-16
BLOCK DIAGRAM
AINL
AINR
Multi-bit
Delta-sigma
Modulator
DSP
Audio
Data
Interface
SDOUT
SCLK
LRCK
Clock Manager
Sample Rate Detector
Control
Interface
MCLK
M1 M0
1
Everest Semiconductor
Confidential
ES7241D
1.
2.
3.
4.
5.
6.
PIN OUT AND DESCRIPTION ................................................................................................ 3
TYPICAL APPLICATION CIRCUIT.......................................................................................... 4
CLOCK MODES AND SAMPLING FREQUENCIES ............................................................... 5
POWER UP AND POWER DOWN .......................................................................................... 5
DIGITAL AUDIO INTERFACE.................................................................................................. 5
ELECTRICAL CHARACTERISTICS ....................................................................................... 6
ABSOLUTE MAXIMUM RATINGS.................................................................................................. 6
RECOMMENDED OPERATING CONDITIONS ................................................................................ 6
ADC ANALOG AND FILTER CHARACTERISTICS AND SPECIFICATIONS .......................................... 6
POWER CONSUMPTION CHARACTERISTICS ................................................................................ 7
SERIAL AUDIO PORT SWITCHING SPECIFICATIONS ..................................................................... 7
7.
8.
PACKAGE ................................................................................................................................ 9
CORPORATE INFORMATION .............................................................................................. 10
Revision 12.0
2
March 2019
Latest datasheet:
www.everest-semi.com
or
info@everest-semi.com
Everest Semiconductor
Confidential
ES7241D
1. PIN OUT AND DESCRIPTION
REFP
M1
M0
MCLK
13
14
15
16
12
11
10
9
GNDA
VDDA
AINR
REFQ
VDDP
SDOUT
GNDD
VDDD
1
2
3
4
ES7241D
8
7
6
5
AINL
RESETb
LRCK
SCLK
Pin Name
M0, M1
MCLK
SCLK
LRCK
SDOUT
RESETb
AINL, AINR
VDDP
VDDD/GNDD
VDDA/GNDA
REFP
REFQ
Pin number
15,14
16
5
6
2
7
8,10
1
4,3
11,12
13
9
Input or Output
I
I
I/O
I/O
O
I
I
I
I
I
O
O
Pin Description
Mode selection
Master clock
Serial data bit clock
Serial data left and right channel frame clock
Serial data output
Active low chip reset (low power)
Analog left and right inputs
Power supply for the digital input and output
Digital power supply
Analog power supply
Filtering capacitor connection
Filtering capacitor connection
Revision 12.0
3
March 2019
Latest datasheet:
www.everest-semi.com
or
info@everest-semi.com
Everest Semiconductor
Confidential
ES7241D
2. TYPICAL APPLICATION CIRCUIT
GND(SYS)
0R
AGND
In the layout, chip is treated as a analog device
AGND AGND
*
1uF
11
VDDA
1
4
AGND
V
DDP
V
DDD
Everest
RESETb
M0
M1
MCL
K
SCLK
LRCK
SDOUT
REFQ
ES7241D
AVDD(+3V3)
100nF
PV
DD(+3V
3)
DVDD(+3V3)
* *
100nF
AGND
AGND
* *
REFP
13
9
1uF
AINR
10
8
1uF
RIN
LIN
1uF
1uF
7
15
14
CPU/DSP
GNDD
GNDA
12
PGND
16
5
6
2
10K
AINL
These formats are I2S (pull up resistor at SDOUT pin)
and left justified (pull down resistor at SDOUT pin)
PV
DD(+3V
3)
For the best performance,decoupling and filtering capacitors should be located as close to the device package as possible
Additional paralle capacitors(typically 0.1 μF) can be used, larger value capacitors(typically 10 μF) would also help
AGND
*
Revision 12.0
4
March 2019
Latest datasheet:
www.everest-semi.com
or
info@everest-semi.com
17
3
Everest Semiconductor
Confidential
ES7241D
3. CLOCK MODES AND SAMPLING FREQUENCIES
The device can work either in master clock mode or slave clock mode by setting mode control
pins M1 and M0 according to Table 1.
Table 1 Mode Control
Pin
M1:M0
Pin Description
00 – master clock mode, single speed mode
01 – master clock mode, double speed mode
10 – master clock mode, quad speed mode
11 – slave clock mode, all speed modes
In master mode, LRCK and SCLK are derived internally from MCLK. The available MCLK/LRCK
ratios are listed in Table 2. SCLK/LRCK ratio is always 64 in master mode.
Table 2 Master Mode Sampling Frequencies and MCLK/LRCK Ratio
Speed Mode
Single Speed
Double Speed
Quad Speed
Sampling Frequency
8kHz – 50kHz
50kHz – 100kHz
100kHz – 200kHz
MCLK/LRCK Ratio
256
128
64
In slave mode, LRCK and SCLK are supplied externally. LRCK and SCLK must be synchronously
derived from the system clock with some specific rates. The device can auto detect MCLK/LRCK
ratio according to Table 3. The device only supports the MCLK/LRCK ratios listed in Table 3. The
SCLK/LRCK ratio is normally 64.
Table 3 Slave Mode Sampling Frequencies and MCLK/LRCK Ratio
Speed Mode
Single Speed
Double Speed
Quad Speed
Sampling Frequency
8kHz – 50kHz
50kHz – 100kHz
100kHz – 200kHz
MCLK/LRCK Ratio
256, 384, 512, 768, 1024
128, 192
64
4. POWER UP AND POWER DOWN
RESETb pin active low will put the device in power down mode. During power-up, RESETb pin
should be hold at low level to keep the device in reset until the power supplies, clocks and mode
selection pins are stable.
5. DIGITAL AUDIO INTERFACE
The device provides many formats of serial audio data interface to the output from the ADC
through LRCK, SCLK and SDOUT pins. These formats are I
2
S (pull up resistor at SDOUT pin) and
left justified (pull down resistor at SDOUT pin). ADC data is out at SDOUT on the falling edge of
Revision 12.0
5
March 2019
Latest datasheet:
www.everest-semi.com
or
info@everest-semi.com
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