Transient Voltage Suppressors
Features
Solid-state silicon-avalanche technology
Low operating and clamping voltage
Up to four I/O Lines of Protection
Ultra low capacitance: 0.35pF typical(I/O to I/O)
Low Leakage
Low operating voltage:5V
Flow-Through design
B0524P
ROHS ROHS
IEC COMPATIBILITY (EN61000-4)
IEC 61000-4-2 (ESD) ±15kV (air), ± 8kV (contact)
IEC 61000-4-4 (EFT) 40A (5/50ns)
IEC 61000-4-5 (Lightning)
3A (8/20μs)
Mechanical Characteristics
DFN-10L package (2.5×1.0×0.58mm)
Molding compound flammability rating: UL 94V-0
Marking: Marking Code
Packaging: Tape and Reel
RoHS/WEEE Compliant
Application
Digital Visual Interface(DVI)
MDDI Ports
DisplayPortTM Interface
PCI Express
High Definition Multi-Media Interface(HDMI)
eSATA Interfaces
Circuit Diagram
Schematic & PIN Configuration
10
9
8
7
6
Pin 1
Pin 2
Pin 4
Pin 5
1
2
3
4
5
3,8
Pin
1,2,4,5
6,7,9,10
3,8
Identificaion
Input Lines
Output Lines
(No Internal Connection)
Ground
4-Line Protection
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Transient Voltage Suppressors
Absolute Maximum Rating
Rating
Peak Pulse Power ( t
p
=8/20μs )
Peak Pulse Current ( t
p
=8/20μs )
ESD per IEC 61000-4-2(Air)
ESD per IEC 61000-4-2(contact)
Operating Temperature
Storage Temperature
Symbol
P
PP
I
pp
Value
100
5
+/-15
+/-8
-55 to + 125
-55 to +150
B0524P
ROHS
Units
Watts
A
V
ESD
T
J
T
STG
kV
°
C
°
C
Electrical Parameters (T=25℃)
Symbol
Parameter
Maximum Reverse Peak Pulse Current
Clamping Voltage @
I
PP
Working Peak Reverse Voltage
I
I
F
I
PP
V
C
V
RW M
I
R
V
BR
I
T
I
F
V
F
1.5KExxA(CA)
Maximum Reverse Leakage Current @
V
RWM
Breakdown Voltage @
I
T
Test Current
Forward Current
Forward Voltage @
I
F
V
C
V
BR
V
RWM
I
R
V
F
I
T
V
I
PP
Electrical Characteristics
Parameter
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamping Voltage
Symbol
V
RWM
V
BR
I
R
Vc
Conditions
Any I/O pin to ground
I
t
= 1mA
Any I/O pin to ground
V
RWM
= 5V, T=25°
C
Any I/O pin to ground
I
pp
=3A, t
p
=8/20µs
Any I/O pin to ground
V
R
= 0V, f = 1MHz
I/O pin to GND
Junction Capacitance
C
j
V
R
= 0V, f = 1MHz
Between I/O pins
0.35
6.0
1
20
0.7
0.5
Minimum
Typical
Maximum
5.0
Units
V
V
µA
V
pF
pF
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Transient Voltage Suppressors
Typical Characteristics
Non-Repetitive Peak Pulse Power vs. Pulse Time
10
110
B0524P
ROHS
Power Derating curve
Peak Pulse Power - Ppp (KW)
% of Rated Power or IP
P
100
90
80
70
60
50
40
30
20
10
0
1
100W 8/20µs
Waveform
0.1
0.01
0.1
1
10
100
1000
0
25
50
75
100
125
150
Pulse Duration -
tp (us)
Ambient Temperature - T
A
(
℃
)
Pulse Waveform
110
100
90
80
70
60
50
40
30
20
10
0
Clamping Voltage vs.Peak Pulse Current
40
35
Clamping Voltage - V
c
(V)
Waveform
Parameters:
tr=8us
td=20us
Percent of I
pp
30
25
Line to Line
e
-t
Td
＝
I
PP
/2
1.5KExxA(CA)
20
15
10
5
0
0
1
2
3
Line to Gnd
Waveform
parameters:
tr=8us td=20us
0
5
10
Time (us)
15
20
25
30
4
5
6
Normalized Capacitance vs. Reverse Voltage
1.5
Insertion Loss S21 - I/O to GND
CH1S21 LOG 6dB / REF 0 dB
Peak Pulse Current - I
pp
(A)
1: -0.086 dB
900 MHz
0
- 6dB
- 12dB
- 18dB
F=1MHz
0
1
2
3
4
5
C ( V
R
) / C
J
( V
R
= 0 )
1.3
1.2
1.0
0.8
0.7
0.6
0.5
0.4
0.3
0.1
0
3
1 2
2: -0.0336dB
1.8 GHz
3: -0.126dB
2.5GHz
- 24dB
- 30dB
- 36dB
- 42dB
- 48dB
1
MHz
10
MHz
100
MHz
1
3
GHz GHz
STOP 3000.000000MHz
Reverse voltage - V
R
(V)
STAR .030MHz
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Transient Voltage Suppressors
Design Recommendations for HDMI protection
B0524P
ROHS ROHS
Adding external ESD protection to HDMI ports can be challenging. First, ESD protection devices have an inherent junction
capacitance. Furthermore, adding even a small amount of capacitance will cause the impedance of the differential pair to
drop. Second, large packages and land pattern requirements cause discontinuities that adversely affect signal integrity. The
B0524P are specifically designed for protection of high-speed interfaces such as HDMI.
8kV ESD contact discharges (±
15kV air
They present <0.5pF capacitance between the pairs while being rated to handle ±
discharge) as outlined in IEC 61000-4-2. Each device is in a leadless SLP package that is less than 1.1mm wide. They are
designed such that the traces flow straight through the device. The narrow package and flow-through design reduces
discontinuities and minimizes impact on signal integrity. This becomes even more critical as signal speeds increase.
Pin Configuration
Figure 1 is an example of how to route the high speed
differential traces through the B0524P . The solid line
represents the PCB trace. The PCB traces are used to
connect the pin pairs for each line (pin 1 to pin 10, pin 2
to pin 9, pin 4 to pin 7, pin 5 to pin 6). For example, line
1 enters at pin 1 and exits at Pin 10 and the PCB trace
connects pin 1 and 10 together. This is true for lines
connected at pins 2, 4, and 5 also. Ground is
1.5KExxA(CA)
connected at pins 3 and 8. One large ground pad should
be used in lieu of two separate pads. The same layout
rules apply for the B0524P
12
11
10
9
8
7
6
5
4
3
2
1
1
HDMI Connector
GND
GND
GND
GND
Figure 1.Flow though layout Using
B0524P
Design Recommendations for HDMI Protection
Good circuit board layout is critical not only for signal integrity, but also for effective suppression of ESD induced transients.
For optimum ESD protection, the following guidelines are recommended:
Place the device as close to the connector as possible.This practice restricts ESD coupling into adjacent traces and
reduces parasitic inductance.
The ESD transient return path to ground should be kept as short as possible.
Whenever possible, use multiple micro vias connected directly from the device ground pad to the ground plane.
Avoid running critical signals near board edges.
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