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RTL8306SD-GR: 产品描述类型：Ethernet Switches 电源电压：1.8V, 3.3V 接口类型：MII, RMII 标准：10/100 Base-T/TX; 产品类别嵌入式处理器和控制器微控制器和处理器; 文件大小1MB，共132页; 制造商瑞昱(REALTEK); 官网地址http://www.realtek.com.tw/; 瑞昱半导体成立于1987年，位于台湾「硅谷」的新竹科学园区，凭借当年几位年轻工程师的热情与毅力，走过艰辛的草创时期到今日具世界领导地位的专业IC设计公司，瑞昱半导体劈荆斩棘，展现旺盛的企图心与卓越的竞争力，开发出广受全球市场肯定与欢迎的高性能、高品质与高经济效益的IC解决方案。瑞昱半导体自成立以来一直保持稳定的成长，归功于瑞昱对产品/技术研发与创新的执着与努力，同时也归因于瑞昱的优良传统。

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RTL8306SD-GR概述

类型：Ethernet Switches 电源电压：1.8V, 3.3V 接口类型：MII, RMII 标准：10/100 Base-T/TX

RTL8306SD-GR规格参数

参数名称	属性值
厂商名称	瑞昱(REALTEK)
包装说明	,
Reach Compliance Code	unknown

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RTL8306SD-GR

RTL8306SDM-GR

RTL8306SD-VC-GR

RTL8306SDM-VC-GR

RTL8306SD-VT-GR

SINGLE-CHIP 6-PORT 10/100MBPS

ETHERNET SWITCH CONTROLLER WITH

DUAL MII/RMII INTERFACES

DATASHEET

Rev. 1.1

22 June 2007

Track ID: JATR-1076-21

Realtek Semiconductor Corp.

No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan

Tel.: +886-3-578-0211. Fax: +886-3-577-6047

www.realtek.com.tw

RTL8306SD/RTL8306SDM

Datasheet

transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any

means without the written permission of Realtek Semiconductor Corp.

TRADEMARKS

Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document

are trademarks/registered trademarks of their respective owners.

DISCLAIMER

Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied,

including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in

this document or in the product described in this document at any time. This document could include

technical inaccuracies or typographical errors.

USING THIS DOCUMENT

This document is intended for use by the software engineer when programming for Realtek

RTL8306SD/RTL8306SDM controller chips. Information pertaining to the hardware design of products

using these chips is contained in a separate document.

Though every effort has been made to ensure that this document is current and accurate, more information

may have become available subsequent to the production of this guide. In that event, please contact your

Realtek representative for additional information that may help in the development process.

REVISION HISTORY

Revision

1.0

1.1

Release Date

2006/11/24

2007/06/22

Summary

First release.

1. Revised Table 1 Pin Assignments Table, page 7 (AI and A0 pin types).

2. Revised Table 5 Port 4 PHY Circuit Interface Pin Definitions, page 16 (Changed

‘DISPORTPRI[4]’ to ‘DISPORTPRI[1]’ for pin 84 description, and changed

‘DISPORTPRI[4]” to ‘DISPORTPRI[0]’ for pin 83 description).

3. Revised Table 8 Serial EEPROM and SMI Pins, page 26 (Changed ‘0 to 25MHz

clock’ to ‘0 to 2.5MHz clock’ for pin 74 description).

4. Revised Table 9 Strapping Pins, page 27 (changed the strapping pin function

description of Pin 111).

5. Revised the MLD description (see section 8.9IGMP & MLD Snooping Function,

page 71).

6. Corrected register names in section 8.14 Port Mirroring, page 80.

7. Added page selection register description (Table 34 PHY 0 Register 16 (Page 0, 1,

2, 3): Global Control 0, page 91).

8. Revised Table 62 DC Characteristics, page 113.

9. Revised Table 65 MII & SMI DC Timing, page 116.

10. Revised section 14 Ordering Information, page 123.

Track ID: JATR-1076-21 Rev. 1.1

6-port 10/100Mbps Single-Chip Dual MII/RMII Switch Controller

RTL8306SD/RTL8306SDM

Datasheet

Table of Contents

GENERAL DESCRIPTION ..............................................................................................................................................1

FEATURES .........................................................................................................................................................................3

SYSTEM APPLICATIONS...............................................................................................................................................4

BLOCK DIAGRAM ...........................................................................................................................................................5

PIN ASSIGNMENTS .........................................................................................................................................................6

5.1.

5.2.

5.3.

6.1.

6.2.

6.3.

6.4.

6.5.

6.6.

6.7.

6.8.

6.9.

6.10.

SSIGNMENTS

IAGRAM

.......................................................................................................................................6

ACKAGE

DENTIFICATION

...........................................................................................................................................6

SSIGNMENTS

ABLE

............................................................................................................................................7

EDIA

ONNECTION

INS

...........................................................................................................................................9

ODE

ONFIGURATION

INS

.......................................................................................................................................9

ORT

4 MAC C

IRCUIT

NTERFACE

INS

......................................................................................................................13

ORT

4 PHY C

IRCUIT

NTERFACE

INS

......................................................................................................................16

ISCELLANEOUS

INS

...............................................................................................................................................23

ORT

LED P

INS

.........................................................................................................................................................24

ERIAL

EEPROM

AND

SMI P

INS

..............................................................................................................................26

TRAPPING

INS

.........................................................................................................................................................27

ORT

TATUS

TRAPPING

INS

..................................................................................................................................29

OWER

INS

...............................................................................................................................................................31

PIN DESCRIPTIONS.........................................................................................................................................................9

BASIC FUNCTIONAL DESCRIPTION........................................................................................................................32

7.1.

WITCH

ORE

UNCTION

VERVIEW

.........................................................................................................................32

7.1.1. Dual MII/RMII .....................................................................................................................................................32

7.1.2. Port0, 1, 2, 3 Status Configuration.......................................................................................................................35

7.1.3. Flow Control ........................................................................................................................................................35

7.1.4. Address Search, Learning, and Aging ..................................................................................................................37

7.1.5. Half Duplex Operation .........................................................................................................................................38

7.1.6. InterFrame Gap....................................................................................................................................................38

7.1.7. Illegal Frame........................................................................................................................................................38

7.2.

HYSICAL

AYER

UNCTIONAL

VERVIEW

...............................................................................................................39

7.2.1. Auto-Negotiation for UTP ....................................................................................................................................39

7.2.2. 10Base-T Transmit Function ................................................................................................................................39

7.2.3. 10Base-T Receive Function ..................................................................................................................................39

7.2.4. Link Monitor.........................................................................................................................................................39

7.2.5. 100Base-TX Transmit Function............................................................................................................................39

7.2.6. 100Base-TX Receive Function..............................................................................................................................40

7.2.7. Power-Down Mode...............................................................................................................................................40

7.2.8. Crossover Detection and Auto Correction ...........................................................................................................40

7.2.9. Polarity Detection and Correction .......................................................................................................................41

7.3.

ENERAL

UNCTION

VERVIEW

................................................................................................................................42

7.3.1. Reset .....................................................................................................................................................................42

7.3.2. Setup and Configuration.......................................................................................................................................43

7.3.3. Serial EEPROM Example: 24LC01/02/04 ...........................................................................................................44

7.3.4. SMI .......................................................................................................................................................................46

7.3.5. Head-Of-Line Blocking ........................................................................................................................................47

7.3.6. Filtering/Forwarding Reserved Control Frame ...................................................................................................47

7.3.7. Loop Detection .....................................................................................................................................................48

7.3.8. MAC Local Loopback Return to External ............................................................................................................49

6-port 10/100Mbps Single-Chip Dual MII/RMII Switch Controller

iii

Track ID: JATR-1076-21 Rev. 1.1

RTL8306SD/RTL8306SDM

Datasheet

7.3.9. Reg.0.14 PHY Digital Loopback Return to Internal.............................................................................................50

7.3.10.

1.8V Power Generation ...................................................................................................................................51

7.3.11.

Crystal/Oscillator ............................................................................................................................................51

ADVANCED FUNCTION DESCRIPTION...................................................................................................................52

8.1.

ACL F

UNCTION

.........................................................................................................................................................52

8.2.

VLAN F

UNCTION

......................................................................................................................................................53

8.2.1. Description ...........................................................................................................................................................53

8.2.2. Port-Based VLAN .................................................................................................................................................55

8.2.3. IEEE 802.1Q Tagged-VID Based VLAN ..............................................................................................................56

8.2.4. VLAN Packet Trap to CPU Port...........................................................................................................................58

8.2.5. PVID.....................................................................................................................................................................58

8.3.

S F

UNCTION

..........................................................................................................................................................59

8.3.1. Bandwidth Control ...............................................................................................................................................59

8.3.2. Priority Assignment ..............................................................................................................................................61

8.4.

OOKUP

ABLE

UNCTION

........................................................................................................................................65

8.4.1. Function Description............................................................................................................................................65

8.4.2. 4-Way Direct Mapping Algorithm ........................................................................................................................65

8.4.3. Lookup and CAM Table Definition ......................................................................................................................65

8.5.

IEEE 802.1

EMARKING

UNCTION

.........................................................................................................................66

8.6.

MIBS F

UNCTION

........................................................................................................................................................67

8.6.1. MIB Counter Description .....................................................................................................................................67

8.6.2. MIB Counter Enable/Clear ..................................................................................................................................68

8.6.3. MIB Counter Timeout...........................................................................................................................................68

8.7.

TORM

ILTER

UNCTION

..........................................................................................................................................68

8.8.

CPU I

NTERRUPT

UNCTION

.......................................................................................................................................70

8.9.

IGMP & MLD S

NOOPING

UNCTION

.........................................................................................................................71

8.10.

CPU T

UNCTION

..................................................................................................................................................73

8.11.

IEEE 802.1

UNCTION

.............................................................................................................................................75

8.11.1.

Port-Based Access Control..............................................................................................................................75

8.11.2.

MAC-Based Access Control.............................................................................................................................76

8.12.

IEEE 802.1D F

UNCTION

............................................................................................................................................77

8.13.

NPUT

& O

UTPUT

ROP

UNCTION

............................................................................................................................78

8.14.

ORT

IRRORING

......................................................................................................................................................80

8.15.

LED F

UNCTION

..........................................................................................................................................................81

8.15.1.

RTL8306SD/RTL8306SDM Controlling LED .................................................................................................83

8.15.2.

CPU Controlling LED .....................................................................................................................................84

REGISTER DESCRIPTIONS.........................................................................................................................................85

9.1.

EGISTER

IST

...........................................................................................................................................................85

9.2.

PHY 0 R

EGISTERS

......................................................................................................................................................87

9.2.1. PHY 0 Register 0 (Page 0, 1, 2, 3): Control.........................................................................................................87

9.2.2. PHY 0 Register 1 (Page 0, 1, 2, 3): Status ...........................................................................................................88

9.2.3. PHY 0 Register 2 (Page 0, 1, 2, 3): PHY Identifier 1 ...........................................................................................88

9.2.4. PHY 0 Register 3 (Page 0, 1, 2, 3): PHY Identifier 2 ...........................................................................................89

9.2.5. PHY 0 Register 4 (Page 0, 1, 2, 3): Auto-Negotiation Advertisement..................................................................89

9.2.6. PHY 0 Register 5 (Page 0, 1, 2, 3): Auto-Negotiation Link Partner Ability.........................................................90

9.2.7. PHY 0 Register 16 (Page 0, 1, 2, 3): Global Control 0........................................................................................91

9.2.8. PHY 0 Register 18 (Page 0, 1): Global Control 2................................................................................................92

9.2.9. PHY 0 Register 19 (Page 0, 1): Global Control 3................................................................................................92

9.2.10.

PHY 0 Register 22 (Page 0, 1): Port 0 Control Register 0..............................................................................93

9.2.11.

PHY 0 Register 24 (Page 0, 1): Port 0 Control Register 1..............................................................................94

9.3.

PHY 1 R

EGISTERS

......................................................................................................................................................94

9.3.1. PHY 1 Register 0 (Page 0, 1, 2, 3): Control.........................................................................................................94

9.3.2. PHY 1 Register 1 (Page 0, 1, 2, 3): Status ...........................................................................................................94

6-port 10/100Mbps Single-Chip Dual MII/RMII Switch Controller

Track ID: JATR-1076-21 Rev. 1.1

RTL8306SD/RTL8306SDM

Datasheet

9.3.3. PHY 1 Register 2 (Page 0, 1, 2, 3): PHY Identifier 1 ...........................................................................................94

9.3.4. PHY 1 Register 3 (Page 0, 1, 2, 3): PHY Identifier 2 ...........................................................................................94

9.3.5. PHY 1 Register 4 (Page 0, 1, 2, 3): Auto-Negotiation Advertisement..................................................................95

9.3.6. PHY 1 Register 5 (Page 0, 1, 2, 3): Auto-Negotiation Link Partner Ability.........................................................95

9.3.7. PHY 1 Register 22 (Page 0, 1): Port 1 Control Register 0...................................................................................95

9.3.8. PHY 1 Register 24 (Page 0, 1): Port 1 Control Register 1...................................................................................95

9.4.

PHY 2 R

EGISTERS

......................................................................................................................................................96

9.4.1. PHY 2 Register 0 (Page 0, 1, 2, 3): Control.........................................................................................................96

9.4.2. PHY 2 Register 1 (Page 0, 1, 2, 3): Status ...........................................................................................................96

9.4.3. PHY 2 Register 2 (Page 0, 1, 2, 3): PHY Identifier 1 ...........................................................................................96

9.4.4. PHY 2 Register 3 (Page 0, 1, 2, 3): PHY Identifier 2 ...........................................................................................96

9.4.5. PHY 2 Register 4 (Page 0, 1, 2, 3): Auto-Negotiation Advertisement..................................................................96

9.4.6. PHY 2 Register 5 (Page 0, 1, 2, 3): Auto-Negotiation Link Partner Ability.........................................................96

9.4.7. PHY 2 Register 22 (Page 0, 1): Port 1 Control Register 0...................................................................................96

9.4.8. PHY 2 Register 23 (Page 0, 1): Global Option Register 1...................................................................................97

9.4.9. PHY 2 Register 24 (Page 0,1): Port 2 Control Register 2....................................................................................97

9.5.

PHY 3 R

EGISTERS

......................................................................................................................................................98

9.5.1. PHY 3 Register 0 (Page 0, 1, 2, 3): Control.........................................................................................................98

9.5.2. PHY 3 Register 1 (Page 0, 1, 2, 3): Status ...........................................................................................................98

9.5.3. PHY 3 Register 2 (Page 0, 1, 2, 3): PHY Identifier 1 ...........................................................................................98

9.5.4. PHY 3 Register 3 (Page 0, 1, 2, 3): PHY Identifier 2 ...........................................................................................98

9.5.5. PHY 3 Register 4 (Page 0, 1, 2, 3): Auto-Negotiation Advertisement..................................................................98

9.5.6. PHY 3 Register 5 (Page 0, 1, 2, 3): Auto-Negotiation Link Partner Ability.........................................................98

9.5.7. PHY 3 Register 16 (Page 0, 1, 2, 3): Switch MAC Address .................................................................................98

9.5.8. PHY 3 Register 17~18 (Page 0, 1): Switch MAC Address ...................................................................................99

9.5.9. PHY 3 Register 22 (Page 0, 1): Port 1 Control Register 0...................................................................................99

9.5.10.

PHY 3 Register 24 (Page 0, 1): Port 3 Control Register 1..............................................................................99

9.6.

PHY 4 R

EGISTERS

....................................................................................................................................................100

9.6.1. PHY 4 Register 0 (Page 0, 1, 2, 3): Control.......................................................................................................100

9.6.2. PHY 4 Register 1 (Page 0, 1, 2, 3): Status .........................................................................................................100

9.6.3. PHY 4 Register 2 (Page 0, 1, 2, 3): PHY Identifier 1 .........................................................................................100

9.6.4. PHY 4 Register 3 (Page 0, 1, 2, 3): PHY Identifier 2 .........................................................................................100

9.6.5. PHY 4 Register 4 (Page 0, 1, 2, 3): Auto-Negotiation Advertisement................................................................100

9.6.6. PHY 4 Register 5 (Page 0, 1, 2, 3): Auto-Negotiation Link Partner Ability.......................................................100

9.6.7. PHY 4 Register 22 (Page 0,1): Port 1 Control Register 0..................................................................................100

9.6.8. PHY 4 Register 24 (Page 0, 1): Port 4 Control Register 1.................................................................................101

9.7.

PHY 5 R

EGISTERS

....................................................................................................................................................102

9.7.1. PHY 5 Register 0 (Page 0, 1, 2, 3): Control.......................................................................................................102

9.7.2. PHY 5 Register 1 (Page 0, 1, 2, 3): Status .........................................................................................................103

9.7.3. PHY 5 Register 2 (Page 0, 1, 2, 3): PHY Identifier 1 .........................................................................................103

9.7.4. PHY 5 Register 3 (Page 0, 1, 2, 3): PHY Identifier 2 .........................................................................................103

9.7.5. PHY 5 Register 4 (Page 0, 1, 2, 3): Auto-Negotiation Advertisement................................................................104

9.7.6. PHY 5 Register 5 (Page 0, 1, 2, 3): Auto-Negotiation Link Partner Ability.......................................................105

9.8.

PHY 6 R

EGISTERS

....................................................................................................................................................106

9.8.1. PHY 6 Register 0 (Page 0, 1, 2, 3): Control.......................................................................................................106

9.8.2. PHY 6 Register 1 (Page 0, 1, 2, 3): Status .........................................................................................................107

9.8.3. PHY 6 Register 2 (Page 0, 1, 2, 3): PHY Identifier 1 .........................................................................................107

9.8.4. PHY 6 Register 3 (Page 0, 1, 2, 3): PHY Identifier 2 .........................................................................................107

9.8.5. PHY 6 Register 4 (Page 0, 1, 2, 3): Auto-Negotiation Advertisement................................................................108

9.8.6. PHY 6 Register 5 (Page 0, 1, 2, 3): Auto-Negotiation Link Partner Ability.......................................................109

9.8.7. PHY 6 Register 22 (Page 0, 1): Port 5 Control Register 0.................................................................................109

9.8.8. PHY 6 Register 24 (Page 0, 1): Port 5 Control Register 1.................................................................................111

10.

10.1.

CHARACTERISTICS...............................................................................................................................................112

LECTRICAL

HARACTERISTICS

AXIMUM

ATINGS

.............................................................................................112

Track ID: JATR-1076-21 Rev. 1.1

6-port 10/100Mbps Single-Chip Dual MII/RMII Switch Controller

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