Datasheet> 器件分类 > 无线/射频/通信> 电信电路> RTL8305SC-LF

文档预览

RTL8305SC-LF: 产品描述类型：Ethernet Switches 电源电压：1.8V, 3.3V 接口类型：MII 标准：100 Base-FX PHY, 10/100 Base-T/TX PHY; 产品类别无线/射频/通信电信电路; 文件大小1MB，共160页; 制造商瑞昱(REALTEK); 官网地址http://www.realtek.com.tw/; 瑞昱半导体成立于1987年，位于台湾「硅谷」的新竹科学园区，凭借当年几位年轻工程师的热情与毅力，走过艰辛的草创时期到今日具世界领导地位的专业IC设计公司，瑞昱半导体劈荆斩棘，展现旺盛的企图心与卓越的竞争力，开发出广受全球市场肯定与欢迎的高性能、高品质与高经济效益的IC解决方案。瑞昱半导体自成立以来一直保持稳定的成长，归功于瑞昱对产品/技术研发与创新的执着与努力，同时也归因于瑞昱的优良传统。

下载文档详细参数全文预览

RTL8305SC-LF概述

类型：Ethernet Switches 电源电压：1.8V, 3.3V 接口类型：MII 标准：100 Base-FX PHY, 10/100 Base-T/TX PHY

RTL8305SC-LF规格参数

参数名称	属性值
厂商名称	瑞昱(REALTEK)
包装说明	QFP, QFP128,.67X.93,20
Reach Compliance Code	unknown
JESD-30 代码	R-PQFP-G128
端子数量	128
最高工作温度	70 °C
最低工作温度
封装主体材料	PLASTIC/EPOXY
封装代码	QFP
封装等效代码	QFP128,.67X.93,20
封装形状	RECTANGULAR
封装形式	FLATPACK
电源	1.8,3.3 V
认证状态	Not Qualified
表面贴装	YES
技术	CMOS
温度等级	COMMERCIAL
端子形式	GULL WING
端子节距	0.5 mm
端子位置	QUAD

RTL8305SC-LF文档预览

下载PDF文档

全文
预览

RTL8305SC

SINGLE-CHIP 5-PORT 10/100MBPS SWITCH

CONTROLLER WITH DUAL MII INTERFACES

DataSheet

Rev. 1.2

02 March 2005

Track ID: JATR-1076-21

RTL8305SC

Datasheet

REVISION HISTORY

Revision Release Date Summary

1.0

2004/06/17 First release.

1.1

2004/06/30 Removed QoS function IPv6 differentiated services and removed Table 147, page 113.

Revised LEDMODE[1:0]=00, in Table 4, page 14, Table 7, page 20, Table 19, page 30, and

Table 69, page 59.

Changed four combinations of LED mode to three combinations of LED display mode, page 3.

1.2

2005/03/02 Corrected section 7.3.10 PHY 2 Register 23: “Port 2 Control Register 1” to “Global Option 1

Revised pull low resister to 1k ohm, Table 5, page 16.

Revised PHY register in Table 64, page 55.

Changed Table 139’s name from PHY 0 to PHY 5, page 87.

Changed Table 140’s name from PHY 8 to PHY 5, page 88.

Add P4PHY_MODE select, in Table 143, page 103.

Corrected Pin52 MTXEN/PRXDV/EN_TRUNK to MTXEN/PRXDV, Pin92

LED_ACT[4]/DISFCAUTOOFF to LED_ACT[4], and Pin115 ENAGBACK/LED_DUP[0] to

LED_DUP[0], in Figure 2, page 7, and Table 1, page 8.

Canceled the description of Pin92 LED_ACT[4]/DISFCAUTOOFF and Pin115

ENAGBACK/LED_DUP[0], section 1, page 2, in Table 9, page 22, and section 8.3.10, page

123.

Reserved PHY 0 Register 18.7 and 18.15, in Table 68, page 58.

Reserved EEPROM Register 4.7, in Table 16, page 28 and Register 5.7, Table 17, page 29.

Corrected QoS based features, section 2, page 4.

Corrected 2SB1188K to 2SB1188 and HVDD18 to DVDD18, in Figure 24, page 132, and

Table 151, page 132.

Corrected “24LC02 must be 1.8Vcompatible” to “24LC02 must be 3.3Vcompatible”, section

8.3.3, page 117.

Corrected TTL Input High Voltage 1.5V to 2.0V and TTL Input Low Voltage 1.0V to 0.8V,

section 9.3, page 134.

Corrected PHY 4 register 18 description, in Table 124, page 81.

Add 100Base-TX TD and RD Differential Output Impedance (return loss) columns and delete

10Base-TX TD and RD Differential Output Impedance (return loss) columns, in Section 9.4

AC Characteristics, page 135.

5-port 10/100Mbps Single-Chip Dual MII Switch Controller

iii

Track ID: JATR-1076-21 Rev. 1.2

RTL8305SC

Datasheet

Table of Contents

GENERAL DESCRIPTION................................................................................................................................................1

FEATURES...........................................................................................................................................................................4

BLOCK DIAGRAM.............................................................................................................................................................6

PIN ASSIGNMENTS ...........................................................................................................................................................7

PIN DESCRIPTIONS ..........................................................................................................................................................9

5.1.

5.2.

5.3.

5.4.

5.5.

5.6.

5.7.

5.8.

5.9.

5.10.

EDIA

ONNECTION

INS

............................................................................................................................................9

ORT

4 C

ONFIGURATION

INS

......................................................................................................................................9

ORT

4 MAC C

IRCUIT

NTERFACE

INS

.....................................................................................................................14

ORT

4 PHY C

IRCUIT

NTERFACE

INS

......................................................................................................................16

ISCELLANEOUS

INS

...............................................................................................................................................19

ORT

LED P

INS

.........................................................................................................................................................20

ERIAL

EEPROM

AND

SMI P

INS

..............................................................................................................................22

TRAPPING

INS

.........................................................................................................................................................22

ORT

TATUS

TRAPPING

INS

...................................................................................................................................24

OWER

INS

...............................................................................................................................................................26

EEPROM DESCRIPTION................................................................................................................................................27

6.1.

ORT

0 R

EGISTERS

.....................................................................................................................................................27

6.1.1.

Global Control Register0 .....................................................................................................................................27

6.1.2.

Global Control Register1 .....................................................................................................................................27

6.1.3.

Global Control Register2 .....................................................................................................................................28

6.1.4.

Global Control Register3 .....................................................................................................................................28

6.1.5.

Global Control Register4 .....................................................................................................................................28

6.1.6.

Global Control Register5 .....................................................................................................................................29

6.1.7.

Global Control Register6 .....................................................................................................................................29

6.1.8.

Global Control Register7 .....................................................................................................................................30

6.1.9.

Port 0 Control 0....................................................................................................................................................30

6.1.10. Port 0 Control 1....................................................................................................................................................31

6.1.11. Port 0 Control 2....................................................................................................................................................31

6.1.12. Port 0 Control 3....................................................................................................................................................31

6.1.13. Port 0 Control 4 & VLAN Entry [A].....................................................................................................................32

6.2.

ORT

1 R

EGISTERS

.....................................................................................................................................................33

6.2.1.

Internal Use Register............................................................................................................................................33

6.2.2.

Port 1 Control 0....................................................................................................................................................33

6.2.3.

Port 1 Control 1....................................................................................................................................................34

6.2.4.

Port 1 Control 2....................................................................................................................................................34

6.2.5.

Port 1 Control 3....................................................................................................................................................34

6.2.6.

Port 1 Control 4 & VLAN Entry [B].....................................................................................................................35

6.3.

ORT

2 R

EGISTERS

.....................................................................................................................................................36

6.3.1.

Internal Use Register............................................................................................................................................36

6.3.2.

Port 2 Control 0....................................................................................................................................................36

6.3.3.

Port 2 Control 1....................................................................................................................................................37

6.3.4.

Reserved ...............................................................................................................................................................37

6.3.5.

Port 2 Control 2 & VLAN Entry [C] ....................................................................................................................38

6.4.

ORT

3 R

EGISTERS

.....................................................................................................................................................39

6.4.1.

Switch MAC Address ............................................................................................................................................39

6.4.2.

Port 3 Control 0....................................................................................................................................................39

6.4.3.

Port 3 Control 1....................................................................................................................................................40

6.4.4.

Reserved ...............................................................................................................................................................40

5-port 10/100Mbps Single-Chip Dual MII Switch Controller

Track ID: JATR-1076-21 Rev. 1.2

RTL8305SC

Datasheet

6.4.5.

Port 3 Control 2 & VLAN Entry [D] ....................................................................................................................40

6.4.6.

Internal Use Register............................................................................................................................................41

6.5.

ORT

4 R

EGISTERS

.....................................................................................................................................................42

6.5.1.

Port 4 Control 0....................................................................................................................................................42

6.5.2.

Port 4 Control 1....................................................................................................................................................42

6.5.3.

Reserved ...............................................................................................................................................................43

6.5.4.

Port 4 Control 2 & VLAN Entry [E].....................................................................................................................43

6.5.5.

Internal Use Register............................................................................................................................................44

6.5.6.

802.1p Base Priority.............................................................................................................................................44

6.6.

VLAN E

NTRIES

.........................................................................................................................................................44

6.6.1.

VLAN Entry [F]....................................................................................................................................................44

6.6.2.

VLAN Entry [G] ...................................................................................................................................................45

6.6.3.

VLAN Entry [H] ...................................................................................................................................................45

6.6.4.

VLAN Entry [I] .....................................................................................................................................................46

6.6.5.

VLAN Entry [J] ....................................................................................................................................................46

6.6.6.

VLAN Entry [K]....................................................................................................................................................47

6.6.7.

VLAN Entry [L] ....................................................................................................................................................47

6.6.8.

VLAN Entry [M] ...................................................................................................................................................48

6.6.9.

VLAN Entry [N]....................................................................................................................................................48

6.6.10. VLAN Entry [O] ...................................................................................................................................................49

6.6.11. VLAN Entry [P]....................................................................................................................................................49

REGISTER DESCRIPTIONS ..........................................................................................................................................50

7.1.

PHY 0 R

EGISTERS

.....................................................................................................................................................53

7.1.1.

PHY 0 Register 0 for Port 0: Control ...................................................................................................................53

7.1.2.

PHY 0 Register 1 for Port 0: Status......................................................................................................................54

7.1.3.

PHY 0 Register 2 for Port 0: PHY Identifier 1 .....................................................................................................54

7.1.4.

PHY 0 Register 3 for Port 0: PHY Identifier 2 .....................................................................................................55

7.1.5.

PHY 0 Register 4 for Port 0: Auto-Negotiation Advertisement ............................................................................55

7.1.6.

PHY 0 Register 5 for Port 0: Auto-Negotiation Link Partner Ability ...................................................................56

7.1.7.

PHY 0 Register 16: Global Control 0...................................................................................................................56

7.1.8.

PHY 0 Register 17: Global Control 1...................................................................................................................58

7.1.9.

PHY 0 Register 18: Global Control 2...................................................................................................................58

7.1.10. PHY 0 Register 19: Global Control 3...................................................................................................................59

7.1.11. PHY 0 Register 22: Port 0 Control Register 0......................................................................................................60

7.1.12. PHY 0 Register 24: Port 0 Control Register 1 & VLAN ID [A] Membership ......................................................61

7.1.13. PHY 0 Register 25: Port 0 Control Register 2 & VLAN ID [A] ...........................................................................61

7.1.14. PHY 0 Register 26: Reserved or VLAN ID [F] Membership................................................................................62

7.1.15. PHY 0 Register 27: Reserved or VLAN ID [F].....................................................................................................62

7.1.16. PHY 0 Register 28: Reserved or VLAN ID [K] Membership................................................................................63

7.1.17. PHY 0 Register 29: Reserved or VLAN ID [K] ....................................................................................................63

7.1.18. PHY 0 Register 30: Reserved or VLAN ID [P] Membership................................................................................64

7.1.19. PHY 0 Register 31: Reserved or VLAN ID [P].....................................................................................................64

7.2.

PHY 1 R

EGISTERS

.....................................................................................................................................................65

7.2.1.

PHY 1 Register 0 for Port 1: Control ...................................................................................................................65

7.2.2.

PHY 1 Register 1 for Port 1: Status......................................................................................................................65

7.2.3.

PHY 1 Register 2 for Port 1: PHY Identifier 1 .....................................................................................................65

7.2.4.

PHY 1 Register 3 for Port 1: PHY Identifier 2 .....................................................................................................65

7.2.5.

PHY 1 Register 4 for Port 1: Auto-Negotiation Advertisement ............................................................................65

7.2.6.

PHY 1 Register 5 for Port 1: Auto-Negotiation Link Partner Ability ...................................................................65

7.2.7.

PHY 1 Register 16~17: Internal Use Register......................................................................................................65

7.2.8.

PHY 1 Register 18~19: Internal Use Register......................................................................................................65

7.2.9.

PHY 1 Register 22: Port 1 Control Register 0......................................................................................................66

7.2.10. PHY 1 Register 23: Global Option Register 0......................................................................................................66

7.2.11. PHY 1 Register 24: Port 1 Control Register 1 & VLAN ID [B] Membership ......................................................66

5-port 10/100Mbps Single-Chip Dual MII Switch Controller

Track ID: JATR-1076-21 Rev. 1.2

推荐资源

走廊灯控制电路图

与逻辑电路

高功率因数开关稳压电源电路

带调节线路的LM378双声道音频功率放大电路

单管恒流充电器电路

875p电脑主板电路图_012

单片机控制GSM模块: 我最近在做单片机控制GSM模块的实验，先做的是单片机通过串口与GSM模块连接，谁知道单片机通过串口发送什么数据可以发送短信呢？希望有高手指点！！！...; lilong8470 无线连接

wince u盘？FAT32？: 尊敬的斑竹及各位大牛们好，小弟一直关注次论坛！现在想问个问题？我的wince5.0系统现在可以识别u盘了，但是如果是FAT32格式的u盘识别时间要1分半钟(有时候可能还长)，如果是FAt格式的u盘很快就 ......; jiaoxianyao 嵌入式系统

求教M3高速AD采样的实现: 本人菜鸟，请高手指点。有个M3(lm3s8962)小系统，要高速进行AD采样搜集，>=600K 采样频率。AD本身采样频率大于100MSPS，再加上SDRAM做数据缓冲。请问用M3能否实现？采用什么接口接受AD数据。S ......; caesun 微控制器 MCU

Windows ce 下的一个简单的驱动设计问题: 我的设备的物理地址基址是0x3800 0000，映射成虚拟地址是0x9000 0000 和0x B000 0000 我设计的流接口驱动程序使用VirtualAlloc（）函数、VirtualCopy（）以及MmMapIoSpace（）函数应该怎么映射 ......; queen 嵌入式系统

【花雕体验】06 搭建行空板开发环境之Thonny编程: 本帖最后由 eagler8 于 2022-6-17 08:56 编辑 1、Thonny是一款轻量级Python编辑器，使用简单容易上手，适合初学者的 Python IDE。官网下载安装即可：https://thonny.org/。 61480 ......; eagler8 MicroPython开源版块

关于COM口的问题: 串口硬件资源的问题,它有个输入/输出范围是03F8-03FF,但是书上好象只说串口芯片8251A只有两个字节的范围,就是命令/状态字缓冲器和数据缓冲器呀,这这么解释呢?还有就是想弄明白输入/输出地址范围 ......; 一无所知嵌入式系统

英飞凌联手Fingerprint Cards推动生物识别卡大规模部署

集成指纹传感器的生物识别支付卡使非接触式支付更加方便、安全和卫生。非接触式支付卡在整个支付交易过程中一直位于持卡人手中，甚至大额支付也无需输入PIN码或签名来授权。英飞凌科技股份公司与FingerprintCardsAB（简称Fingerprints，STO:FING-B）携手合作，实现该全新解决方案的大规模部署。非接触式支付安全控制器与指纹传感器（包括相关软件）领域的全球领导企业旨...[详细]
单板计算机在物联网时代大有可为

爱立信预计，2022年，物联网设备数量将达到15亿台，到2023年，工业物联网连接数将超过35亿台。嵌入式计算机和物联网的爆炸式增长推动物联网应用数量不断增加。可以受益于物联网设备使用的工业部门包括交通工程、数据记录、石油和天然气勘探等。但也有一些挑战需要克服。交通工程面临的挑战根据美国海关和边境保护局的统计数据，绝大多数非法毒品运输，都是利用汽车、飞机和船只通过既定的入境口岸走私的...[详细]
Commvault Hedvig分布式存储平台又有新功能

球云和本地环境数据管理软件的公认领导者Commvault（纳斯达克代码：CVLT）近日在CommvaultFutureReady大会上宣布推出Hedvig分布式存储平台（HedvigDistributedStoragePlatform）的全新增强功能，用于在混合云和多云环境下运行Kubernetes。Kubernetes已迅速发展成为应用程序现代化的标准容器基础设施平台。企业需要确...[详细]
拓扑光子学—半导体技术发展的高速公路

翻译自——spectrum激光、芯片和量子电路都可以从这种模糊的现象中受益自2007年拓扑绝缘体首次问世以来，这种内部绝缘、外部导电的新型材料激发了研究人员对其在电子领域的潜力的兴趣。然而，一种相关但更模糊的材料——拓扑光子，可能会首先达到实际应用。拓扑学是数学的一个分支，研究形状的哪些方面能承受变形。例如，一个形状像环的物体可以变形成杯子形状，环上的孔形成了杯子柄上的孔...[详细]
Intel以全新理念迎接新黄金十年的挑战

2020年注定是特殊的一年，由于新冠病毒在全球的肆虐，全球经济似乎被按下了暂停键，对于半导体行业也是一个不小的打击。根据全球领先的信息技术研究和顾问公司Gartner预测，由于新冠疫情对半导体供需的影响，2020年全球半导体收入预计将下降0.9%，远低于上一季度所预测的增长12.5%。然而，疫情带来了严峻的考验，也带来了经济结构调整的加速。如何把握机遇，开创新格局？近期，英特尔...[详细]
QCC5100系列助力万宝龙打造首款无线智能耳机，体验悦耳音质

近日，万宝龙正式推出品牌首款无线智能耳机，该产品搭载了Qualcomm旗舰级低功耗蓝牙耳机解决方案——QCC5100系列。凭借QCC5100系列的低功耗、高性能和高集成度等优势，以及对QualcommaptXAdaptive和语音助手等功能的支持，万宝龙无线智能耳机将为全球商旅人士带来优雅舒适、功能强大、音质卓越的沉浸式聆听体验。对于通...[详细]
5G边缘计算到底怎么用

边缘计算一经问世，立刻吸引了ICT行业的广泛关注。根据国际调研机构Garter公司的报告，到2022年，超过一半的企业数据将在边缘计算平台产生和处理。这意味着，边缘计算很有可能成为和云计算分庭抗礼的一种全新商业模式和生态，蕴藏着巨大的市场潜力和商业机会。但是，伴随着边缘计算美好憧憬的，是对这种创新模式的未知和困惑。人们非常好奇，电信运营商的5G边缘计算究竟该如何进行部署？又该如何进行...[详细]
大联大诠鼎推出耳机头盔一体化设计解决方案

致力于亚太地区市场的领先半导体元器件分销商---大联大控股宣布，其旗下诠鼎推出基于高通（Qualcomm）QCC3024的耳机头盔一体化设解决方案。随着生活节奏的加快，人们通过手机APP点餐越来越多，外卖配送员必须使用手机接单并和客户联系，才能将外卖快速准确的送达。由于送餐时间有限，配送员经常会在骑行中与客户电话确认，这是非常危险的。如果将耳机和头盔做成一体化，配送员在骑行中只需要...[详细]
Google秋季发布会—AI串联全家桶

Google今日在纽约召开秋季新品发布会，推出旗下新款智能手机Pixel4系列手机、PixelBuds耳机、Pixelbook笔记本等新品。这是一次硬件大会，Google几乎更新了自己全线硬件产品。第一个登场的硬件是Google耳机GooglePixelBuds是Google自家的无线耳机，其地位大致等于苹果的AirPods。Google硬件带头人Rick在台上介绍这安...[详细]
识微见远，英特尔三大战略引领“万物智能互联”变革

以“识微见远”为主题的2019英特尔物联网峰会在厦门举行。会上，英特尔系统介绍了其布局物联网领域的三大支柱战略，讲述了近年来为推动全球物联网从边缘到云的部署而做出的努力。当前，英特尔正全面发力物联网领域，凭借其领先的技术和产品组合以及独特的端到端解决方案，打造广泛而多元的创新生态，携手合作伙伴促进人工智能与物联网的融合发展，引领“万物智能互联”的行业变革。英特尔公司高级副总裁兼物...[详细]
清微智能全球首款可重构超低功耗语音AI芯片开始量产

最近，脱胎于清华大学微电子所Thinker团队的AI芯片创企清微智能迎来新进展：全球首款可重构超低功耗语音人工智能（AI）芯片TX210已实现规模化量产，于6月中旬正式交付市场，而此时清微智能距成立还不到1年。这是一款语音SoC芯片，针对手机、可穿戴设备、智能家居等多种应用场景的智能终端产品开发，工作功耗不超过2mW，语音活动检测（VAD）功耗小于100uW，延时不到10ms。...[详细]
Xilinx荣登《麻省理工科技评论》全球50家最聪明公司

自适应和智能计算的全球领先企业赛灵思公司（Xilinx,Inc.，（NASDAQ:XLNX））今天宣布，公司首次荣登新鲜出炉的全球权威榜单—2019《麻省理工科技评论》“50家聪明公司”（TR50）榜单。TR50是全球范围内最权威的技术商业类榜单之一，同时也是“一份技术如何改造世界的指南”。此份榜单是由《麻省理工科技评论》中美编辑部，以及来自全球学术界、产业界、投资界的特邀顾问团共同进...[详细]
国民技术与海尔、有方科技三方合作，让工业互联网更安全

7月2日，国民技术股份有限公司（简称“国民技术”、“公司”）与海尔数字科技有限公司（简称“海尔数字”）、深圳市有方科技股份有限公司（简称“有方科技”）在青岛签署了三方战略合作协议，三方将在工业互联网与物联网等领域开展深度合作，共同打造国内首个工业互联网国密安全体系，为海尔工业互联网平台COSMOPlat提供边缘层硬件国密安全解决方案和国密安全云解决方案。国民技术股份有限公司董事长、总经理孙...[详细]
OPEN MIND最新版本的 hyperMILL® CAD/CAM 套件

最新版本的hyperMILL®CAD/CAM套件2019.2拥有一系列新功能，包括高精度3D精加工、5轴切向加工、高性能车削和新的CAM专用CAD技术。OPENMIND将越来越多先前需要额外CAD操作步骤的功能直接集成到CAM策略中，以进一步加快编程速度。“3DZ轴外形偏置精加工”中的新功能可确保表面超光滑，公差处于微米级别切向加工：使...[详细]
智能物流机器人公司Geek+完成C1轮融资

7月11日消息，智能物流机器人公司极智嘉Geek+CEO兼创始人郑勇在香港举行的RISE科技与人工智能峰会上透露，极智嘉Geek+已经成功完成C1轮主力融资。本轮融资由知名投资机构GGV（纪源资本）和D1领投，美国华平投资集团等现有股东投资人继续跟投，并由泰合资本担任独家财务顾问。据了解，Geek+主要致力于提供机器人智能物流解决方...[详细]

小广播

热搜元器件