TX50N06
N channel 60V MOSFET
Description
The TX50N06 is the N-Channel logic enhancement
mode power field effect transistors are produced using high cell
density, DMOS trench technology.This high density process is
especially tailored to minimize on-state resistance.These
devices are particularly suited for low voltage application.
Features
V
DS
R
DS(on)Max.
I
D
60V
20mΩ
50A
●
High density cell design for ultra low
R
DS(on)
●
Excellent package
dissipation
for
good
heat
Pin configuration
Order Number
TX50N06
Package
TO-252
2
1
3
TO-252
Maximum Ratings (
Tc = 25℃
Parameter
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
Pulsed Drain Current
Power Dissipation
unless otherwise noted*)
Symbol
V
DSS
V
GSS
Ratings
60
±20
50*
35.4*
90
85
0.3
245
-55~+175
℃
Units
V
V
A
A
A
W
Tc=25℃
Tc=100℃
Tc=25℃
Derate above 25℃
I
D
I
DM
P
D
E
AS
T
J
,T
stg
Single pulse avalanche energy
（note
1）
Operating Junction and Storage Temperature Range
* Dran current limited by maximum junction temperature.
1：EAS condition:L=0.5mH, V
DD
=30V, R
G
=25Ω,T
J
=25℃.
Thermal Characteristics
Parameter
Thermal resistance, case to sink typ.
Thermal resistance junction to case.
Thermal resistance junction to ambient.
Symbol
RthCS
RthJC
RthJA
Ratings
0.5
3.3
110
Units
℃/W
℃/W
℃/W
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TX50N06
N channel 60V MOSFET
Electrical characteristics
Symbol
STATIC
BV
DSS
V
GS(th)
I
GSS
I
DSS
R
DS(ON)
V
SD
Parameter
(TA =25℃ Unless Otherwise Specified)
Test Conditions
Min.
Typ.
Max.
Units
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
Drain-Source On-Resistance
Diode Forward Voltage
V
GS
=0V, I
D
=250μA
V
DS
=V
GS
, I
D
=250μA
V
DS
=0V, V
GS
=±20V
V
DS
=60V, V
GS
=0V
V
GS
=10V, I
D
=20A
I
S
=20A, V
GS
=0V
60
1.4
—
—
—
—
—
—
—
—
14
—
—
2.5
±100
1
20
1.2
V
V
nA
μA
mΩ
V
DYNAMIC
Q
g
Q
gs
Q
gd
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
t
rr
Q
rr
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
Reverse Recovery Time
Reverse Recovery Charge
TJ = 25°C, IF =20A
di/dt = 100A/μs
V
DD
=30V, R
G
=3Ω
R
L
=6.7Ω,V
GS
=10V,
V
DS
=30V, V
GS
=0V, f=1MHz
V
DS
=30V, V
GS
=10V, I
D
=20A
—
—
—
—
—
—
—
—
—
—
—
—
50
6
15
2050
158
120
7..4
5.1
28.2
5.5
28
40
—
—
—
—
—
—
—
—
—
—
—
—
nS
nC
ns
pF
nC
Notes :a. Pulse test:pulse width 300 us,duty cycle 2% ,Guaranteed by design,not subject to production testing.
b. XDSSEMI reserves the right to improve product design,functions and reliability without notice.
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TX50N06
N channel 60V MOSFET
Typical Characteristics
Output Characteristics
(TJ =25℃ Noted)
RDS(on) vs. JunctionTemperature
Drain-Source Voltage,V
DS
(V)
Junction Temperature,T
j
(℃)
Transfer Characteristics
Gate Charge
Gate-to-Source Voltage,V
GS
(V)
Gate Charge,Qg(nC)
R
DS(on)
vs.
Drain Current
Source-to- Drain Diode Forward
Drain Current,I
D
(A)
Source-Drai Voltage,V
SD
(V)
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TX50N06
N channel 60V MOSFET
Capacitance vs. Drain Source Voltage
BV
DSS
vs. Junction Temperature
Drain Source Voltage V
DS
(V)
Junction Temperature,T
J
(℃)
Safe Operation Area
B
VDSS
vs Junction Temperature
Drain-Source Voltage,V
DS
(V)
Junction Temperature,T
J
(℃)
Normalized Thermal Transient Impedance,Junction to Ambient
Square Wave Pulse Duration,t1(sec)
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TX50N06
N channel 60V MOSFET
TO-252
Unit：mm
Making
LOGO
PART NUMBER
"D" TO-252
"A" GRANDE
HS50N06
DA
YMM
DATE CODE:
"Y"=LAST DIGIT OF
CALENDAR YEAR
"WW"=WORK WEEK
V1.0
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NXP MCU
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