TVS/ESD Arrays - RLST23AxxxV Series
Features
• 400 Watts peak pulse power (tp = 8/20μs)
• Transient protection for high speed data lines to
IEC 61000-4-2 (ESD) ±15kV (air), ±8kV (contact)
IEC 61000-4-4 (EFT) 40A (5/50ns)
IEC 61000-4-5 (Lightning) 24A (8/20μs)
• Two devices protect two high-speed line pairs
• Low leakage current
• Low operating and clamping voltages
• Solid-state EPD TVS process technology
Mechanical Characteristics
•
SOT-23
package
• Molding compound flammability rating: UL 94V-0
• Packaging: Tape and Reel per EIA 481
• Lead Finish: Matte tin
• RoHS Compliant
Pinout and Functional Block Diagram
Applications
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Cellular Handsets and Accessories
Portable Electronics
Industrial Controls
Set-Top Box
Servers, Notebook, and Desktop PC
Life Support Note
• Not Intended for Use in Life Support or Life
Saving Applications
• The products shown herein are not designed
for use in life sustaining or life saving
applications unless otherwise expressly indicated
SOT23 (Top View)
Circuit Protection
System
Specifications are subject to change without notice.
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TVS/ESD Arrays - RLST23AxxxV Series
Applications Information
Device Connection Options
The RLST23A032V and RLST23A362V series is
designed to protect one bidirectional or two unidirectional
data or I/O lines operating at 5 to 36 volts. Connection
options are as follows:
• Bidirectional: Pin 1 is connected to the data line
and pin 2 is connected to ground (Since the device
is symmetrical, these connections may be reversed).
The ground connection should be made directly to a
ground plane. The path length should be kept as short
as possible to minimize parasitic inductance. Pin 3 is not
connected.• Unidirectional: Data lines are connected to
pin 1 and pin 2. Pin 3 is connected to ground. For best
results, this pin should be connected directly to a ground
plane on the board. The path length should be kept as
short as possible to minimize parasitic inductance. Circuit
Board Layout Recommendations for Suppression of ESD.
Good circuit board layout is critical for the suppression
of fast rise-time transients such as ESD. The following
guidelines are recommended (Refer to application note
SI99-01 for more detailed information):
• Place the TVS near the input terminals or connectors
to restrict transient coupling.
• Minimize the path length between the TVS and the
protected line.
• Minimize all conductive loops including power and
ground loops.
• The ESD transient return path to ground should be kept
as short as possible.
• Never run critical signals near board edges.
• Use ground planes whenever possible.
Matte Tin Lead Finish
Matte tin has become the industry standard lead-free
replacement for SnPb lead finishes. A matte tin finish is
composed of 100% tin solder with large grains. Since
the solder volume on the leads is small compared to the
solder paste volume that is placed on the and pattern
of the PCB, the reflow profile will be determined by
the requirements of the solder paste. Therefore, these
devices are compatible with both lead-free and SnPb
assembly techniques. In addition, unlike other lead-free
compositions, matte tin does not have any added alloys
that can cause degradation of the solder joint.
Device Schematic & Pin Configuration
RS-232 Transceiver P rotection Example
Circuit Protection
System
Specifications are subject to change without notice.
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