74HC165
8-BIT PARALLEL-LOAD SHIFT REGISTERS
1
FEATURES
Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 80-μA Max I
CC
Typical t
pd
= 13 ns
±4-mA Output Drive at 5 V
Low Input Current of 1
μA
Max
Complementary Outputs
Direct Overriding Load (Data) Inputs
Gated Clock Inputs
Parallel-to-Serial Data Conversion
DESCRIPTION
The ’HC165 devices are 8-bit parallel-load shift
registers that, when clocked, shift the data toward a
serial (Q
H
) output. Parallel-in access to each stage is
provided by eight individual direct data (A−H) inputs
that are enabled by a low level at the shift/load
(SH/LD) input. The ’HC165 devices also feature a
clock-inhibit (CLK INH) function and a complementary
serial (QH) output.
Clocking is accomplished by a low-to-high transition
of the clock (CLK) input while SH/LD is held high and
CLK INH is held low. The functions of CLK and CLK
INH are interchangeable. Since a low CLK and a low-
to-high transition of CLK INH also accomplish
clocking, CLK INH should be changed to the high
level only while CLK is high. Parallel loading is
inhibited when SH/LD is held high. While SH/LD is
low, the parallel inputs to the register are enabled
independently of the levels of the CLK, CLK INH, or
serial (SER) inputs.
SN54HC165 . . . FK PACKAGE
(TOP VIEW)
•
•
•
•
•
•
•
•
•
•
SH/LD
CLK
E
F
G
H
Q
H
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
CLK INH
D
C
B
A
SER
Q
H
E
F
NC
G
H
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
CLK
SH/LD
NC
V
CC
CLK INH
D
C
NC
B
A
NC − No internal connection
1
SN54HC165 . . . J or W PACKAGE
SN74HC165 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
Q
H
GND
NC
Q
H
SER
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2018 AUG
74HC165
FUNCTION TABLE
INPUTS
SH/LD
L
H
H
H
H
(1)
CLK
X
H
X
L
↑
CLK INH
X
X
H
↑
L
FUNCTION
Parallel load
No change
No change
Shift
(1)
Shift
(1)
Shift = content of each internal register shifts toward serial output
Q
H
. Data at SER is shifted into the first register.
LOGIC DIAGRAM (POSITIVE LOGIC)
A
SH/LD
1
11
B
12
C
13
D
14
E
3
F
4
G
5
H
6
CLK INH
CLK
15
2
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
9
Q
H
SER
10
7
Q
H
Pin numbers shown are for theD, DB, J, N, NS, PW and W packages.
,
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2
2018 AUG
74HC165
TYPICAL SHIFT, LOAD, AND INHIBIT SEQUENCE
CLK
CLK INH
SER
L
SH/LD
A
H
L
H
L
H
B
C
Data
Inputs
D
E
F
G
H
Q
H
Q
H
L
H
H
H
L
Inhibit
Load
H
L
L
H
H
L
L
H
H
L
L
H
H
L
Serial Shift
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3
2018 AUG
74HC165
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
V
CC
I
IK
I
OK
I
O
Supply voltage range
Input clamp current
Output clamp current
Continuous output current
Continuous current through V
CC
UNITS
V
mA
mA
mA
mA
°C/W
°C/W
°C/W
°C/W
°C/W
°C
−0.5
to 7
V
I
< 0 or V
I
> V
CC
V
O
= 0 to V
CC
or GND
D package
DB Package
(2)
(2)
±20
±20
±25
±50
73
82
67
64
108
–65 to 150
V
O
< 0 or V
O
> V
CC
θ
JA (3)
Package thermal impedance
N package
NS package
PW package
T
stg
(1)
(2)
(3)
Storage temperature range
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS
(1)
over operating free-air temperature range (unless otherwise noted)
SN54HC165
MIN
V
CC
V
IH
Supply voltage
V
CC
= 2 V
High-level input voltage
V
CC
= 4.5 V
V
CC
= 6 V
V
CC
= 2 V
V
IL
V
I
V
O
Δt/Δv
(2)
SN74HC165
MAX
6
MIN
2
1.5
3.15
4.2
0.5
1.35
1.8
0.5
1.35
1.8
0
0
V
CC
V
CC
1000
500
400
−40
125
NOM
5
MAX
6
NOM
5
UNIT
V
2
1.5
3.15
4.2
V
Low level input voltage
V
CC
= 4.5 V
V
CC
= 6 V
0
0
V
CC
= 2 V
V
Input voltage
Output voltage
V
CC
V
CC
1000
500
400
V
V
Input transition rise/fall time
V
CC
= 4.5 V
V
CC
= 6 V
−55
ns
T
A
Operating free-air temperature
125
°C
(1)
(2)
All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number
SCBA004.
If this device is used in the threshold region (from V
IL
max = 0.5 V to V
IH
min = 1.5 V), there is a potential to go into the wrong state from
induced grounding, causing double clocking. Operating with the inputs at t
t
= 1000 ns and V
CC
= 2 V does not damage the device;
however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
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4
2018 AUG
74HC165
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
V
CC
MIN
2V
I
OH
=
−20 μA
V
OH
V
I
= V
IH
or V
IL
I
OH
=
−4
mA
I
OH
=
−5.2
mA
I
OL
= 20
μA
V
OL
V
I
= V
IH
or V
IL
I
OL
= 4 mA
I
OL
= 5.2 mA
I
I
I
CC
C
i
V
I
= V
CC
or 0
V
I
= V
CC
or 0,
I
O
= 0
4.5 V
6V
4.5 V
6V
2V
4.5 V
6V
4.5 V
6V
6V
6V
2 V to 6
V
3
1.9
4.4
5.9
3.98
5.48
T
A
= 25°C
TYP
1.998
4.499
5.999
4.3
5.8
0.002
0.001
0.001
0.17
0.15
±0.1
0.1
0.1
0.1
0.26
0.26
±100
8
10
MAX
SN54HC165
–55°C TO 125°C
MIN
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±1000
160
10
MAX
SN74HC165
–40°C TO 85°C
MIN
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±1000
80
10
MAX
Recommended
SN74HC165
–40°C TO 125°C
MIN
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±1000
160
10
nA
μA
pF
V
V
MAX
UNIT
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5
2018 AUG
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