HG25Q40
3V 4M -BIT SERIAL NOR FLASH WITH DUAL AND QUAD SPI
FEATURES
Low power supply operation
- Single 2.3V-3.6V supply
4M/2M bit Serial Flash
- 4 M-bit/512K-byte/2,048 pages
- 2 M-bit/256K-byte/1,024 pages
- 256 bytes per programmable page
- Uniform 4K-byte Sectors, 32K/64K-byte Blocks
New Family of SpiFlash Memories
- Standard SPI: CLK, CS#, DI, DO, WP#,
HOLD# / RESET#
- Dual SPI: CLK, CS#, DI, DO, WP#, HOLD# /
RESET#
- Quad SPI: CLK, CS#, IO0, IO1, IO2, IO3
- Software & Hardware Reset
- Auto-increment Read capability
Temperature Ranges
- Industrial (-40°C to +85°C)
- Extended (-20°C to +85°C)
Low power consumption
- 9 mA typical active current
- 2 uA typical power down current
Efficient “Continuous Read” and Quad Read
- Continuous Read with 8/16/32/64-Byte Wrap
- As few as 8 clocks to address memory
- Quad Peripheral Interface reduces instruction
overhead
Flexible Architecture with 4KB sectors
- Sector Erase (4K-bytes)
- Block Erase (32K/64K-bytes)
- Page Program up to 256 bytes
- More than 100K erase/program cycles
- More than 20-year data retention
Advanced Security Feature
- Software and Hardware Write-Protect
- Power Supply Lock-Down and OTP
protection
- Top/Bottom, Complement array protection
- 64-Bit Unique ID for each device
- Discoverable parameters(SFDP) register
- 3X256-Bytes Security Registers with OTP
locks
- Volatile & Non-volatile Status Register Bits
High performance program/erase speed
- Page program time: 400us typical
- Sector erase time: 35ms typical
- Block erase time: 200ms typical
- Chip erase time: 10 Seconds typical
Package Options
- 8-pin SOIC 150/208-mil
- 8-pad WSON 6x5-mm
- 8-pin PDIP 300-mil
- All Pb-free packages are RoHS compliant
GENERAL DESCRIPTION
The HG25Q40/20 of non-volatile flash memory device supports the standard Serial Peripheral Interface
(SPI). Traditional SPI single bit serial input and output (Single I/O or SIO) is supported as well as optional two
bit (Dual I/O or DIO) and four bit (quad I/O) serial protocols. This multiple width interface is called SPI Multi-I/O
or MIO.
The SPI protocols use only 4 to 6 signals:
Chip Select (CS#)
Serial Clock (CLK)
Serial Data
- IO0 (DI)
- IO1 (DO)
- IO2 (WP#)
- IO3 (HOLD# / RESET#)
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HG25Q40
The HG25Q 40/20 support the standard Serial Peripheral Interface (SPI), Dual/Quad I/O SPI as well as
2-clocks instruction cycle Quad Peripheral Interface : Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1
(DO), I/O2 (WP#), and I/O3 (HOLD# / RESET#). SPI clock frequencies of up to 104MHz are supported
allowing equivalent clock rates of 208MHz (104MHz x 2) for Dual I/O and 44MHz (104MHz x 4) for Quad I/O
when using the Fast Read Dual/Quad I/O . These transfer rates can outperform standard Asynchronous 8 and
16-bit Parallel Flash memories. The Continuous Read Mode allows for efficient memory access with as few as
8-clocks of instruction-overhead to read a 24-bit address, allowing true XIP (execute in place) operation.
A Hold pin, Write Protect pin and programmable write protection, with top or bottom array control, provide
further control flexibility. Additionally, the device supports JEDEC standard manufacturer and device ID and
SFDP Register, a 64-bit Unique Serial Number and three 256-bytes Security Registers.
The HG25Q40/20 provides an ideal storage solution for systems with limited space, signal connections,
and power. These memories' flexibility and performance is better than ordinary serial flash devices. They are
ideal for code shadowing to RAM, executing code directly (XIP), and storing reprogrammable data.
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BLOCK DIAGRAM
Figure 2.1 Block Diagram
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CONNECTION DIAGRAMS
Figure 3.1 8-pin SOP (150/208mil)/ PDIP (300mil)
Figure 3.2 8-Contact 6 x 5 mm WSON
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SIGNAL DESCRIPTIONS
Table 4.1 Pin Descriptions
Symbol
CLK
DI(IO0)
DO(IO1)
CS#
WP#(IO2)
(3)
HOLD# / RESET#
(3)
(IO3)
V
CC
GND
Pin Name
Serial Clock Input
Serial Data Input(Data input output 0)
(1)
Serial Data Output(Data input output 1)
(1)
Chip Enable
Write Protect (Data input output 2)
(2)
Hold or Reset input(Data input output 3)
(2)
Power Supply (2.3-3.6V)
Ground
Notes:
(1)IO0 and IO1 are used for Standard and Dual SPI instructions.
(2)IO0—IO3 are used for QUAD SPI instructions.
(3)WP# and HOLD# / RESET# functions are only available for Standard and Dual SPI.
Serial Data Input (DI) / IO0
The SPI Serial Data Input (DI) pin is used to transfer data serially into the device. It receives instructions,
address and data to be programmed. Data is latched on the rising edge of the Serial Clock (CLK) input pin.
The DI pin becomes IO0 - an input and output during Dual and Quad commands for receiving instructions,
address, and data to be programmed (values latched on rising edge of serial CLK clock signal) as well as
shifting out data (on the falling edge of CLK).
Serial Data Output (DO) / IO1
The SPI Serial Data Output (DO) pin is used to transfer data serially out of the device. Data is shifted out
on the falling edge of the Serial Clock (CLK) input pin. DO becomes IO1 - an input and output during Dual and
Quad commands for receiving instructions, addresses, and data to be programmed (values latched on rising
edge of serial CLK clock signal) as well as shifting out data (on the falling edge of CLK).
Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI
Mode")
Chip Select (CS#)
The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device is
deselected and the Serial Data Output pins are at high impedance.
When deselected, the devices power consumption will be at standby levels unless an internal erase,
program or status register cycle is in progress. When CS# is brought low the device will be selected, power
consumption will increase to active levels and instructions can be written to and data read from the device.
After power-up, CS# must transition from high to low before a new instruction will be accepted.
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嵌入式系统
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