1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ40C/20C/10C/05C
GD25LQ40C/20C/10C/05C
DATASHEET
1
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ40C/20C/10C/05C
Contents
1
2
3
4
5
6
7
FEATURES
.........................................................................................................................................................4
GENERAL DESCRIPTION
................................................................................................................................5
MEMORY ORGANIZATION
...............................................................................................................................7
DEVICE OPERATION
...................................................................................................................................... 10
DATA PROTECTION
........................................................................................................................................ 11
STATUS REGISTER.........................................................................................................................................
16
COMMANDS DESCRIPTION
.......................................................................................................................... 18
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.15
7.16
7.17
7.18
7.19
7.20
7.21
7.22
7.23
7.24
7.25
7.26
7.27
7.28
7.29
7.30
7.31
7.32
W
RITE
E
NABLE
(WREN) (06H) ................................................................................................................................ 22
W
RITE
D
ISABLE
(WRDI) (04H) ................................................................................................................................ 22
W
RITE
E
NABLE FOR
V
OLATILE
S
TATUS
R
EGISTER
(50H) ................................................................................................. 22
R
EAD
S
TATUS
R
EGISTER
(RDSR) (05H
OR
35H) .......................................................................................................... 23
W
RITE
S
TATUS
R
EGISTER
(WRSR) (01H) ................................................................................................................... 23
R
EAD
D
ATA
B
YTES
(READ) (03H)............................................................................................................................. 24
R
EAD
D
ATA
B
YTES AT
H
IGHER
S
PEED
(F
AST
R
EAD
) (0BH) .............................................................................................. 24
D
UAL
O
UTPUT
F
AST
R
EAD
(3BH) .............................................................................................................................. 25
Q
UAD
O
UTPUT
F
AST
R
EAD
(6BH) ............................................................................................................................. 26
D
UAL
I/O F
AST
R
EAD
(BBH) .................................................................................................................................... 26
Q
UAD
I/O F
AST
R
EAD
(EBH) ................................................................................................................................... 28
S
ET
B
URST WITH
W
RAP
(77H) ................................................................................................................................. 29
P
AGE
P
ROGRAM
(PP) (02H) .................................................................................................................................... 30
Q
UAD
P
AGE
P
ROGRAM
(32H) .................................................................................................................................. 31
S
ECTOR
E
RASE
(SE) (20H) ....................................................................................................................................... 32
32KB B
LOCK
E
RASE
(BE) (52H) ............................................................................................................................... 32
64KB B
LOCK
E
RASE
(BE) (D8H)............................................................................................................................... 32
C
HIP
E
RASE
(CE) (60/C7H) ..................................................................................................................................... 33
E
NABLE
/D
ISABLE
SO
TO
O
UTPUT
RY/BY# (ESRY/DSRY) (70H/80H) ........................................................................... 33
D
EEP
P
OWER
-D
OWN
(DP) (B9H) ............................................................................................................................. 34
R
ELEASE FROM
D
EEP
P
OWER
-D
OWN AND
R
EAD
D
EVICE
ID (RDI) (ABH) ......................................................................... 35
R
EAD
M
ANUFACTURE
I
D
/ D
EVICE
I
D
(REMS) (90H) .................................................................................................... 36
R
EAD
M
ANUFACTURE
ID/ D
EVICE
ID D
UAL
I/O (92H) ................................................................................................. 37
R
EAD
M
ANUFACTURE
ID/ D
EVICE
ID Q
UAD
I/O (94H)................................................................................................. 38
R
EAD
I
DENTIFICATION
(RDID) (9FH) ......................................................................................................................... 39
R
EAD
U
NIQUE
ID (4BH) .......................................................................................................................................... 40
P
ROGRAM
/E
RASE
S
USPEND
(PES) (75H) ................................................................................................................... 40
P
ROGRAM
/E
RASE
R
ESUME
(PER) (7AH) ................................................................................................................... 41
E
RASE
S
ECURITY
R
EGISTERS
(44H) ............................................................................................................................ 41
P
ROGRAM
S
ECURITY
R
EGISTERS
(42H) ....................................................................................................................... 42
R
EAD
S
ECURITY
R
EGISTERS
(48H) ............................................................................................................................. 42
E
NABLE
R
ESET
(66H)
AND
R
ESET
(99H) ..................................................................................................................... 43
2
1.8V Uniform Sector
Dual and Quad Serial Flash
7.33
8
GD25LQ40C/20C/10C/05C
R
EAD
S
ERIAL
F
LASH
D
ISCOVERABLE
P
ARAMETER
(5AH) ................................................................................................. 44
ELECTRICAL CHARACTERISTICS
.............................................................................................................. 49
8.1
8.2
8.3
8.4
8.5
8.6
POWER-ON TIMING ........................................................................................................................................... 49
I
NITIAL
D
ELIVERY
S
TATE
........................................................................................................................................... 49
A
BSOLUTE
M
AXIMUM
R
ATINGS
................................................................................................................................. 49
C
APACITANCE
M
EASUREMENT
C
ONDITIONS
................................................................................................................. 50
DC CHARACTERISTICS......................................................................................................................................... 51
AC CHARACTERISTICS ......................................................................................................................................... 54
9
ORDERING INFORMATION
............................................................................................................................ 61
9.1
V
ALID
P
ART
N
UMBERS
............................................................................................................................................ 62
PACKAGE INFORMATION
......................................................................................................................... 67
P
ACKAGE
SOP8 150MIL ........................................................................................................................................ 67
P
ACKAGE
SOP8 208MIL ........................................................................................................................................ 68
P
ACKAGE
VSOP8 150MIL ...................................................................................................................................... 69
P
ACKAGE
VSOP8 208MIL ...................................................................................................................................... 70
P
ACKAGE
TSSOP8 173MIL..................................................................................................................................... 71
P
ACKAGE
USON8 (3*2
MM
, 0.45
MM THICKNESS
) ...................................................................................................... 72
P
ACKAGE
USON8 (3*3
MM
).................................................................................................................................... 73
P
ACKAGE
USON8 (3*4
MM
).................................................................................................................................... 74
P
ACKAGE
USON8 (4*4
MM
, 0.45
MM THICKNESS
) ...................................................................................................... 75
P
ACKAGE
WSON8 (6*5
MM
) .............................................................................................................................. 76
10
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
10.10
11
REVISION HISTORY
.................................................................................................................................... 77
3
1.8V Uniform Sector
Dual and Quad Serial Flash
1 FEATURES
◆
4M/2M/1M/512K-bit Serial Flash
- 512K/256K/128K/64K-byte
- 256 bytes per programmable page
◆
Standard, Dual, Quad SPI
- Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#
- Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD#
- Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3
◆
High Speed Clock Frequency
- 104MHz for fast read with 30PF load
- Dual I/O Data transfer up to 208Mbits/s
- Quad I/O Data transfer up to 416Mbits/s
◆
Allows XIP (execute in place) Operation
- Continuous Read With 8/16/32/64-byte Wrap
◆
Software/Hardware Write Protection
- Write protect all/portion of memory via software
- Enable/Disable protection with WP# Pin
- Top/Bottom Block protection
◆
Minimum 100,000 Program/Erase Cycles
GD25LQ40C/20C/10C/05C
◆
Fast Program/Erase Speed
- Page Program time: 0.7ms typical
- Sector Erase time: 40ms typical
- Block Erase time: 0.15/0.18s typical
- Chip Erase time: 1.25/0.8/0.4s/0.2s typical
◆
Flexible Architecture
- Uniform Sector of 4K-byte
- Uniform Block of 32/64K-byte
- Erase/Program Suspend/Resume
◆
Low Power Consumption
-1uA typical deep power down current
-9uA typical standby current
◆
Advanced security Features
-128-bit Unique ID
-3*512-Byte Security Registers With OTP Lock
◆
Single Power Supply Voltage
- Full voltage range: 1.65~2.1V
◆
Data Retention
- 20-year data retention typical
4
1.8V Uniform Sector
Dual and Quad Serial Flash
2 GENERAL DESCRIPTION
GD25LQ40C/20C/10C/05C
The GD25LQ40C/20C/10C/05C (4M/2M/1M/512K-bit) Serial flash supports the standard Serial Peripheral Interface (SPI),
and supports the Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and I/O3
(HOLD#). The Dual I/O data is transferred with speed of 208Mbits/s, the Quad I/O & Quad output data is transferred with
speed of 416Mbits/s.
CONNECTION DIAGRAM
CS#
SO
(IO1)
WP#
(IO2)
VSS
1
2
Top View
3
4
8
7
6
5
VCC
HOLD#
(IO3)
SCLK
SI
(IO0)
CS#
SO
(IO1)
WP#
(IO2)
VSS
1
2
Top View
3
4
8–LEAD WSON/USON
8
7
6
5
VCC
HOLD#
(IO3)
SCLK
SI
(IO0)
8–LEAD VSOP/SOP
PIN DESCRIPTION
Pin Name
CS#
SO (IO1)
WP# (IO2)
VSS
SI (IO0)
SCLK
HOLD# (IO3)
VCC
I/O
I
I/O
I/O
I
I/O
I/O
Description
Chip Select Input
Data Output (Data Input Output 1)
Write Protect Input (Data Input Output 2)
Ground
Data Input (Data Input Output 0)
Serial Clock Input
Hold Input (Data Input Output 3)
Power Supply
Note: CS# must be driven high if chip is not selected. Please don’t leave CS# floating any time after power is on.
5