3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q127C
GD25Q127C
DATASHEET
1
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q127C
Contents
1.
2.
3.
4.
5.
6.
7.
FEATURES
................................................................................................................................................................ 4
GENERAL DESCRIPTION
...................................................................................................................................... 5
MEMORY ORGANIZATION
.................................................................................................................................... 8
DEVICE OPERATION
.............................................................................................................................................. 9
DATA PROTECTION
.............................................................................................................................................. 11
STATUS REGISTER
............................................................................................................................................... 13
COMMANDS DESCRIPTION
............................................................................................................................... 15
7.1.
7.2.
7.3.
7.4.
7.5.
7.6.
7.7.
7.8.
7.9.
7.10.
7.11.
7.12.
7.13.
7.14.
7.15.
7.16.
7.17.
7.18.
7.19.
7.20.
7.21.
7.22.
7.23.
7.24.
7.25.
7.26.
7.27.
7.28.
7.29.
7.30.
7.31.
7.32.
W
RITE
E
NABLE
(WREN) (06H) ......................................................................................................................... 18
W
RITE
D
ISABLE
(WRDI) (04H) ......................................................................................................................... 18
W
RITE
E
NABLE FOR
V
OLATILE
S
TATUS
R
EGISTER
(50H) .................................................................................. 18
R
EAD
S
TATUS
R
EGISTER
(RDSR) (05H
OR
35H
OR
15H) .................................................................................. 19
W
RITE
S
TATUS
R
EGISTER
(WRSR) (01H
OR
31H
OR
11H) ................................................................................ 20
R
EAD
D
ATA
B
YTES
(READ) (03H) .................................................................................................................... 20
R
EAD
D
ATA
B
YTES AT
H
IGHER
S
PEED
(F
AST
R
EAD
) (0BH) .............................................................................. 21
D
UAL
O
UTPUT
F
AST
R
EAD
(3BH) ...................................................................................................................... 21
Q
UAD
O
UTPUT
F
AST
R
EAD
(6BH) ..................................................................................................................... 22
D
UAL
I/O F
AST
R
EAD
(BBH) ............................................................................................................................. 22
Q
UAD
I/O F
AST
R
EAD
(EBH) ............................................................................................................................. 23
Q
UAD
I/O W
ORD
F
AST
R
EAD
(E7H) .................................................................................................................. 25
S
ET
B
URST WITH
W
RAP
(77H) ........................................................................................................................... 26
P
AGE
P
ROGRAM
(PP) (02H) ............................................................................................................................... 27
Q
UAD
P
AGE
P
ROGRAM
(32H)............................................................................................................................. 27
S
ECTOR
E
RASE
(SE) (20H) ................................................................................................................................. 28
32KB B
LOCK
E
RASE
(BE) (52H) ....................................................................................................................... 29
64KB B
LOCK
E
RASE
(BE) (D8H) ...................................................................................................................... 29
C
HIP
E
RASE
(CE) (60/C7H) ............................................................................................................................... 30
D
EEP
P
OWER
-D
OWN
(DP) (B9H) ....................................................................................................................... 30
R
ELEASE FROM
D
EEP
P
OWER
-D
OWN AND
R
EAD
D
EVICE
ID (RDI) (ABH) ........................................................ 31
R
EAD
M
ANUFACTURE
ID/ D
EVICE
ID (REMS) (90H)........................................................................................ 32
R
EAD
M
ANUFACTURE
ID/ D
EVICE
ID D
UAL
I/O (92H)...................................................................................... 32
R
EAD
M
ANUFACTURE
ID/ D
EVICE
ID Q
UAD
I/O (94H) ..................................................................................... 33
R
EAD
I
DENTIFICATION
(RDID) (9FH) ................................................................................................................ 34
P
ROGRAM
/E
RASE
S
USPEND
(PES) (75H) ........................................................................................................... 35
P
ROGRAM
/E
RASE
R
ESUME
(PER) (7AH) ........................................................................................................... 36
E
RASE
S
ECURITY
R
EGISTERS
(44H) ................................................................................................................... 36
P
ROGRAM
S
ECURITY
R
EGISTERS
(42H).............................................................................................................. 37
R
EAD
S
ECURITY
R
EGISTERS
(48H)..................................................................................................................... 37
E
NABLE
R
ESET
(66H)
AND
R
ESET
(99H) ............................................................................................................ 38
R
EAD
S
ERIAL
F
LASH
D
ISCOVERABLE
P
ARAMETER
(5AH) ................................................................................. 39
2
3.3V Uniform Sector
Dual and Quad Serial Flash
8.
8.1.
8.2.
8.3.
8.4.
8.5.
8.6.
9.
GD25Q127C
ELECTRICAL CHARACTERISTICS
................................................................................................................... 44
POWER-ON TIMING ....................................................................................................................................... 44
INITIAL DELIVERY STATE ........................................................................................................................... 44
ABSOLUTE MAXIMUM RATINGS ............................................................................................................... 44
CAPACITANCE MEASUREMENT CONDITIONS ....................................................................................... 45
DC CHARACTERISTICS................................................................................................................................. 46
AC CHARACTERISTICS................................................................................................................................. 48
ORDERING INFORMATION
................................................................................................................................. 52
9.1.
V
ALID
P
ART
N
UMBERS
...................................................................................................................................... 53
PACKAGE INFORMATION
............................................................................................................................... 54
P
ACKAGE
SOP8 208MIL ................................................................................................................................... 54
P
ACKAGE
VSOP8 208MIL................................................................................................................................. 55
P
ACKAGE
SOP16 300MIL.................................................................................................................................. 56
P
ACKAGE
DIP8 300MIL .................................................................................................................................... 57
P
ACKAGE
WSON 8 (6*5
MM
) ............................................................................................................................. 58
P
ACKAGE
WSON 8 (8*6
MM
) ............................................................................................................................. 59
P
ACKAGE
TFBGA-24BALL (6*4
BALL ARRAY
) ................................................................................................ 60
REVISION HISTORY
.......................................................................................................................................... 61
10.
10.1.
10.2.
10.3.
10.4.
10.5.
10.6.
10.7.
11.
3
3.3V Uniform Sector
Dual and Quad Serial Flash
1. FEATURES
◆
GD25Q127C
128M-bit Serial Flash
-16384K-byte
-256 bytes per programmable page
◆
Fast Program/Erase Speed
-Page Program time: 0.6ms typical
-Sector Erase time: 50ms typical
-Block Erase time: 0.2/0.3s typical
◆
Standard, Dual, Quad SPI
-Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#/ RESET#
-Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD#/ RESET#
-Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3
◆
-Chip Erase time: 60s typical
Flexible Architecture
-Uniform Sector of 4K-byte
-Uniform Block of 32/64k-byte
◆
High Speed Clock Frequency
-104MHz for Standard and Dual SPI fast read with 30PF load
-Dual I/O Data transfer up to 208Mbits/s
-Quad I/O Data transfer up to 416Mbits/s
◆
Low Power Consumption
-25mA maximum active current
-1uA maximum power down current
Advanced Security Features
(1)
-3*1024-Byte Security Registers With OTP Locks
-Discoverable parameters(SFDP) register
◆
Software/Hardware Write Protection
-Write protect all/portion of memory via software
-Enable/Disable protection with WP# Pin
-Top/Bottom Block protection
◆
◆
◆
Single Power Supply Voltage
-Full voltage range:2.7~3.6V
Allows XIP(execute in place)operation
-Continuous Read With 8/16/32/64-byte Wrap
◆
Package Information
-SOP8 (208mil)
-VSOP8 (208mil)
◆
Minimum 100,000 Program/Erase Cycles
◆
Data retention
-20-year data retention typical
-SOP16 (300mil)
-DIP8 (300mil)
-WSON8 (8*6mm)
-WSON8 (6*5mm)
-TFBGA-24(6*4 ball array)
Note: 1.Please contact GigaDevice for details.
4
3.3V Uniform Sector
Dual and Quad Serial Flash
2. GENERAL DESCRIPTION
GD25Q127C
The GD25Q127C (128M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the
Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and I/O3 (HOLD#/ RESET#). The
Dual I/O data is transferred with speed of 208Mbits/s and the Quad I/O & Quad output data is transferred with speed of
416Mbits/s.
CONNECTION DIAGRAM
CS#
SO
(IO1)
WP#
(IO2)
VSS
1
2
Top View
3
4
8
7
6
5
VCC
HOLD#/
RESET#
(IO3)
SCLK
SI
(IO0)
CS#
SO
(IO1)
WP#
(IO2)
1
2
Top View
3
8
VCC
HOLD#/
7 RESET#
(IO3)
6 SCLK
5
SI
(IO0)
VSS 4
8–LEAD WSON
8–LEAD SOP/VSOP/DIP
HOLD#/
RESET#
VCC
(1)
1
2
3
4
16
SCLK
SI
(IO0)
Top View
4
NC
3
NC
2
NC
1
NC
NC
NC
NC
NC
NC
VSS
15
14
13
VCC
NC
NC
NC
NC
WP#
HOLD#/
NC
(IO2)
RESET#
(IO3)
NC
NC
NC
Top View
NC
NC
5
6
12
11
NC SI(IO0) NC
CS# SO(IO1)
NC
NC
NC
SCLK
CS#
SO
(IO1)
7
8
10
9
VSS
WP#
(IO2)
A
B
C
D
E
F
16-LEAD SOP
24-BALL TFBGA
Note:
(1) Only for special order, Pin 3 of 16-LEAD SOP package is RESET# pin. Please contact GigaDevice for detail.
5