ESMT
Mobile SDRAM
M52S32162A
1M x 16Bit x 2Banks
Mobile Synchronous DRAM
FEATURES
2.5V power supply
LVCMOS compatible with multiplexed address
Dual banks operation
MRS cycle with address key programs
-
CAS Latency ( 2 & 3 )
-
Burst Length (1, 2, 4, 8 & full page)
-
Burst Type (Sequential & Interleave)
EMRS cycle with address key programs.
All inputs are sampled at the positive going edge of the
system clock
Burst Read Single-bit Write operation
Special Function Support.
-
PASR (Partial Array Self Refresh )
-
TCSR (Temperature compensated Self Refresh)
-
DS (Driver Strength)
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle)
GENERAL DESCRIPTION
The M52S32162A is 33,554,432 bits synchronous high data
rate Dynamic RAM organized as 2 x 1,048,576 words by 16
bits, fabricated with high performance CMOS technology.
Synchronous design allows precise cycle control with the use
of system clock I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst
length and programmable latencies allow the same device to
be useful for a variety of high bandwidth, high performance
memory system applications.
ORDERING INFORMATION
Product ID
M52S32162A -6TG
Max
Freq.
Package
Comments
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
166MHz 54 Pin TSOP(II)
M52S32162A -7.5TG 133MHz 54 Pin TSOP(II)
M52S32162A -10TG
M52S32162A -6BG
100MHz 54 Pin TSOP(II)
166MHz
54 Ball BGA
54 Ball BGA
54 Ball BGA
M52S32162A -7.5BG 133MHz
M52S32162A -10BG
100MHz
PIN CONFIGURATION (TOP VIEW)
54 Pin TSOP(II)
V
DD
DQ0
V
DDQ
DQ1
DQ2
V
SSQ
DQ3
DQ4
V
DDQ
DQ5
DQ6
V
SSQ
DQ7
V
DD
LDQM
WE
CAS
RAS
CS
NC
BA
A
10
/AP
A
0
A
1
A
2
A
3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ1 5
V
S SQ
DQ1 4
DQ1 3
V
DDQ
DQ1 2
DQ1 1
V
S SQ
DQ1 0
DQ9
V
DDQ
DQ8
V
SS
NC
UDQM
CLK
CKE
NC
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
54 Ball BGA(8mmx8mm)
1
A
B
C
D
E
F
G
H
J
V
S S
DQ14
DQ12
2
D Q1 5
D Q1 3
DQ11
3
V
S S Q
4
5
6
7
V
DDQ
8
DQ0
DQ2
DQ4
DQ6
9
V
DD
DQ1
V
DDQ
V
SS Q
V
DDQ
V
S S Q
V
DDQ
V
S SQ
DQ3
DQ5
DQ10
DQ9
DQ8
NC
CLK
A11
V
SS
V
DD
LDQM
DQ7
WE
CS
A1 0
V
DD
UDQM
CKE
A9
CAS
BA
A0
A3
RAS
NC
NC
A8
V
SS
A7
A5
A6
A4
A1
A2
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Dec. 2009
Revision
:
1.5
1/32
ESMT
FUNCTIONAL BLOCK DIAGRAM
M52S32162A
Bank Select
Data Input Register
LWE
LDQM
1M x 16
1M x 16
DQi
CLK
ADD
Column Decoder
Latency & Burst Length
LCKE
Programming Register
LRAS
LCBR
LWE
LCAS
LWCBR
LDQM
Timing Register
CLK
CKE
L(U)DQM
CS
RAS
CAS
WE
PIN FUNCTION DESCRIPTION
Pin
CLK
CS
CKE
A0 ~ A11
BA
RAS
CAS
WE
Name
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM.
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row / column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11, column address : CA0 ~ CA7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with
CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS ,
WE
active.
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when L(U)DQM active.
Column Address Strobe
Write Enable
Data Input / Output Mask
L(U)DQM
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Dec. 2009
Revision
:
1.5
2/32
ESMT
DQ0 ~ 15
VDD/VSS
VDDQ/VSSQ
N.C/RFU
Data Input / Output
Power Supply/Ground
Data Output Power/Ground
No Connection/
Reserved for Future Use
M52S32162A
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved
noise immunity.
This pin is recommended to be left No Connection on the device.
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to V
SS
Voltage on V
DD
supply relative to V
SS
Storage temperature
Power dissipation
Short circuit current
Symbol
V
IN
,V
OUT
V
DD
,V
DDQ
T
STG
P
D
I
OS
Value
-1.0 ~ 3.6
-1.0 ~ 3.6
-55 ~ + 150
0.7
50
Unit
V
V
°
C
W
mA
Note:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= 0
°C
~ 70
°C
)
Parameter
Supply voltage
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Output leakage current
Note:
Symbol
V
DD
,V
DDQ
V
IH
V
IL
V
OH
V
OL
I
IL
I
OL
Min
2.3
0.8 x V
DDQ
-0.3
V
DDQ -
0.2
-
-5
-5
Typ
2.5
2.5
0
-
-
-
-
Max
2.7
V
DDQ
+0.3
0.3
-
0.2
5
5
Unit
V
V
V
V
V
uA
uA
Note
1
2
I
OH
=-0.1mA
I
OL
= 0.1mA
3
4
1.V
IH
(max) = 3.0V AC for pulse width
≤
3ns acceptable.
2.V
IL
(min) = -1.0V AC for pulse width
≤
3ns acceptable.
3.Any input 0V
≤
V
IN
≤
V
DDQ
, all other pins are not under test = 0V.
4.Dout is disabled, 0V
≤
V
OUT
≤
V
DDQ
.
CAPACITANCE
(V
DD
= 2.5V, T
A
= 25
°C
, f = 1MHz)
Pin
CLOCK
RAS , CAS ,
WE
, CS , CKE, LDQM,
UDQM
ADDRESS
DQ0 ~DQ15
Symbol
C
CLK
C
IN
C
ADD
C
OUT
Min
-
-
-
-
Max
4.0
4.0
4.0
6.0
Unit
pF
pF
pF
pF
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Dec. 2009
Revision
:
1.5
3/32
ESMT
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, T
A
= 0
°C
~ 70
°C
)
Parameter
Operating Current
(One Bank Active)
Precharge Standby
Current in power-down
mode
Precharge Standby
Current in non
power-down mode
Symbol
Test Condition
Burst Length = 1
t
RC
≥
t
RC
(min), t
CC
≥
t
CC
(min), I
OL
= 0mA
CKE
≤
V
IL
(max), t
CC
=15ns
CKE
≤
V
IL
(max), CLK
≤
V
IL
(max), t
CC
=
∞
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
=15ns
Input signals are changed one time during 30ns
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
CKE
≤
V
IL
(max), t
CC
=15ns
CKE
≤
V
IL
(max), CLK
≤
V
IL
(max), t
CC
=
∞
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
=15ns
Input signals are changed one time during 2clks
All other pins
≥
V
DD
-0.2V or
≤
0.2V
I
CC3NS
I
CC4
I
CC5
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
I
OL
= 0mA, Page Burst
All Band Activated, t
CCD
= t
CCD
(min)
t
RFC
≥
t
RFC
(min)
TCSR range
Self Refresh Current
I
CC6
CKE
≤
0.2V
2 Banks
1 Bank
Deep Power Down
Current
I
CC7
CKE
≤
0.2V
100
40
M52S32162A
Version
-6
100
-7.5
80
0.3
0.2
9
-10
60
Unit Note
mA
mA
mA
mA
1
I
CC1
I
CC2P
I
CC2PS
I
CC2N
I
CC2NS
Active Standby Current
in power-down mode
Active Standby Current
in non power-down
mode
(One Bank Active)
I
CC3P
I
CC3PS
I
CC3N
8
2
1.5
15
mA
mA
mA
8
80
40
60
40
70
200
180
15
mA
mA
1
Operating Current
(Burst Mode)
Refresh Current
mA
2
45
180
160
°C
uA
uA
Note:
1.Measured with outputs open. Addresses are changed only one time during t
CC
(min).
2.Refresh period is 64ms. Addresses are changed only one time during t
CC
(min).
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Dec. 2009
Revision
:
1.5
4/32
ESMT
AC OPERATING TEST CONDITIONS
(V
DD
=2.5V
±
0.2V, T
A
= 0 °C ~ 70 °C )
Parameter
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
0.9 x V
DDQ
/ 0.2
0.5 x V
DDQ
tr / tf = 1 / 1
0.5 x V
DDQ
See Fig.2
M52S32162A
Unit
V
V
ns
V
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
@ Operating
@ Auto refresh
Symbol
t
RRD
(min)
t
RCD
(min)
t
RP
(min)
t
RAS
(min)
t
RAS
(max)
t
RC
(min)
t
RFC
(min)
t
CDL
(min)
t
RDL
(min)
t
BDL
(min)
t
CCD
(min)
t
REF
(max)
CAS latency=3
CAS latency=2
60
60
Version
-6
12
18
18
36
-7.5
15
22.5
22.5
45
100
67.5
67.5
1
2
1
1
64
2
1
90
90
-10
20
30
30
50
Unit
ns
ns
ns
ns
us
ns
ns
CLK
CLK
CLK
CLK
ms
ea
1
1,6
2
2
2
3
5
4
Note
1
1
1
1
Row cycle time
Last data in to new col. Address delay
Last data in to row precharge
Last data in to burst stop
Col. Address to col. Address delay
Refresh period (4,096 rows)
Number of valid output data
Note:
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks.
5. A maximum of eight consecutive AUTO REFRESH commands (with t
RFCmin
) can be posted to any given SDRAM, and
the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is
8x15.6
μ
s.)
6. A new command may be given t
RFC
after self refresh exit.
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Dec. 2009
Revision
:
1.5
5/32
消费电子
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
