ESMT
Mobile SDRAM
FEATURES
2.5V power supply
LVCMOS compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
- CAS Latency (2 & 3)
- Burst Length (1, 2, 4, 8 & full page)
- Burst Type (Sequential & Interleave)
EMRS cycle with address
All inputs are sampled at the positive going edge of the
system clock
Special function support
-
PASR (Partial Array Self Refresh)
-
TCSR (Temperature Compensated Self Refresh)
-
DS (Driver Strength)
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle)
M52S128168A (2E)
2M x 16 Bit x 4 Banks
Mobile Synchronous DRAM
ORDERING INFORMATION
Product ID
M52S128168A-5BG2E
M52S128168A-6BG2E
M52S128168A-7BG2E
Max Freq.
200MHz
166MHz
143MHz
Package
54 Ball FBGA
54 Ball FBGA
54 Ball FBGA
Comments
Pb-free
Pb-free
Pb-free
GENERAL DESCRIPTION
The M52S128168A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152
words by 16 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are
possible on every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies
allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
BALL CONFIGURATION (TOP VIEW)
(BGA54, 8mmX8mmX1mm Body, 0.8mm Ball Pitch)
1
A
VSS
2
DQ15
3
VSSQ
4
5
6
7
VDDQ
8
DQ0
9
VDD
B
DQ14
DQ13
VDDQ
VSSQ
DQ2
DQ1
C
DQ12
DQ11
VSSQ
VDDQ
DQ4
DQ3
D
DQ10
DQ9
VDDQ
VSSQ
DQ6
DQ5
E
DQ8
NC
VSS
VDD
LDQM
DQ7
F
UDQM
CLK
CKE
CAS
RAS
WE
G
NC
A11
A9
BA0
BA1
CS
H
A8
A7
A6
A0
A1
A10
J
VSS
A5
A4
A3
A2
VDD
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2012
Revision: 1.0
1/47
ESMT
FUNCTIONAL BLOCK DIAGRAM
CLK
CKE
Address
Mode
Register
Clock
Generator
M52S128168A (2E)
Bank D
Bank C
Bank B
Row Decoder
Row
Address
Buffer
&
Refresh
Counter
Bank A
Sense Amplifier
Command Decoder
Control Logic
CS
RAS
CAS
WE
Input & Output
Buffer
Latch Circuit
Column
Address
Buffer
&
Refresh
Counter
L(U)DQM
Column Decoder
Data Control Circuit
DQ
BALL FUNCTION DESCRIPTION
PIN
CLK
CS
CKE
A0 ~ A11
BA0 , BA1
NAME
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
INPUT FUNCTION
Active on the positive going edge to sample all inputs
Disables or enables device operation by masking or enabling all
inputs except CLK , CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior new command.
Disable input buffers for power down in standby.
Row / column address are multiplexed on the same pins.
Row address : RA0~RA11, column address : CA0~CA8
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
Latches row addresses on the positive going edge of the CLK with
RAS
Row Address Strobe
RAS low.
Enables row access & precharge.
Latches column address on the positive going edge of the CLK with
CAS
Column Address Strobe
CAS low.
Enables column access.
Enables write operation and row precharge.
WE
Write Enable
Data Input / Output Mask
Data Input / Output
Power Supply / Ground
Data Output Power / Ground
No Connection
Latches data in starting from CAS ,
WE
active.
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when L(U)DQM active.
Data inputs / outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
This pin is recommended to be left No Connection on the device.
L(U)DQM
DQ0 ~ DQ15
VDD / VSS
VDDQ / VSSQ
NC
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2012
Revision: 1.0
2/47
ESMT
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Voltage on any pin relative to V
SS
Voltage on V
DD
supply relative to V
SS
Operation ambient temperature
Storage temperature
Power dissipation
Short circuit current
Note:
SYMBOL
V
IN
, V
OUT
V
DD
, V
DDQ
T
A
T
STG
P
D
I
OS
M52S128168A (2E)
VALUE
-1.0 ~ 3.6
-1.0 ~ 3.6
0 ~ +70
-55 ~ +150
1
50
UNIT
V
V
°
C
°
C
W
mA
Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITION
Recommended operating conditions (Voltage referenced to V
SS
= 0V)
PARAMETER
Supply voltage
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
SYMBOL
V
DD
, V
DDQ
V
IH
V
IL
V
OH
V
OL
I
IL
MIN
2.3
0.8 x V
DDQ
-0.3
V
DDQ
-0.2
-
-2
TYP
2.5
2.5
0
-
-
-
MAX
2.7
V
DDQ
+0.3
0.3
-
0.2
2
UNIT
V
V
V
V
V
NOTE
1
2
3
I
OH
= -0.1mA
I
OL
= 0.1mA
4
μ
A
Note:
1. under all conditions, V
DDQ
must be less than or equal to V
DD
.
2. V
IH
(max) = 3.0V. The overshoot voltage duration is
≤
3ns.
3. V
IL
(min) = -1.0V. The undershoot voltage duration is
≤
3ns.
4. Any input 0V
≤
V
IN
≤
V
DDQ
.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs.
CAPACITANCE
(V
DD
= 2.5V, T
A
= 25
°
C , f = 1MHz)
PARAMETER
Input capacitance (A0 ~ A11, BA0 ~ BA1)
Input capacitance
(CLK, CKE, CS , RAS , CAS ,
WE
&
L(U)DQM)
Data input/output capacitance (DQ0 ~ DQ15)
C
IN2
2
4
pF
SYMBOL
C
IN1
MIN
2
MAX
4
UNIT
pF
C
OUT
3
5
pF
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2012
Revision: 1.0
3/47
ESMT
DC CHARACTERISTICS
Recommended operating condition unless otherwise noted
Parameter
Operating Current
(One Bank Active)
Precharge Standby
Current in power-down
mode
Precharge Standby
Current in non
power-down mode
Symbol
Test Condition
Burst Length = 1
t
RC
≥
t
RC
(min), t
CC
≥
t
CC
(min), I
OL
= 0mA
CKE
≤
V
IL
(max), t
CC
=15ns
CKE
≤
V
IL
(max), CLK
≤
V
IL
(max), t
CC
=
∞
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
=10ns
Input signals are changed one time during 20ns
I
CC2NS
Active Standby Current
in power-down mode
Active Standby Current
in non power-down
mode
(One Bank Active)
Operating Current
(Burst Mode)
Refresh Current
I
CC3P
I
CC3PS
I
CC3N
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
CKE
≤
V
IL
(max), t
CC
=15ns
CKE
≤
V
IL
(max), CLK
≤
V
IL
(max), t
CC
=
∞
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
=15ns
Input signals are changed one time during 2clks
All other pins
≥
V
DD
-0.2V or
≤
0.2V
I
CC3NS
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
I
OL
= 0mA, Page Burst
All Bank Activated, t
CCD
= t
CCD
(min)
t
RFC
≥
t
RFC
(min)
TCSR range
Full array
Self Refresh Current
I
CC6
CKE
≤
0.2V
1/2 array
1/4 array
1/8 array
Deep Power Down
Current
I
CC7
CKE
≤
0.2V
M52S128168A (2E)
Version
-5
55
-6
50
900
900
8
-7
45
Unit Note
I
CC1
I
CC2P
I
CC2PS
I
CC2N
mA
uA
uA
mA
1
1
2
mA
mA
1
15
mA
5
100
70
45
900
800
700
600
10
90
65
80
60
85
1000
900
mA
mA
mA
°C
1
2
I
CC4
I
CC5
uA
800
700
uA
Note:
1.Measured with outputs open. Addresses are changed only one time during t
CC
(min).
2.Refresh period is 64ms. Addresses are changed only one time during t
CC
(min).
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2012
Revision: 1.0
4/47
ESMT
AC OPERATING TEST CONDITIONS
(V
DD
=2.5V
±
0.2V)
Parameter
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
0.9 x V
DDQ
/ 0.2
0.5 x V
DDQ
tr / tf = 1 / 1
0.5 x V
DDQ
See Fig.2
M52S128168A (2E)
Unit
V
V
ns
V
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
@ Operating
@ Auto refresh
Symbol
t
RRD
(min)
t
RCD
(min)
t
RP
(min)
t
RAS
(min)
t
RAS
(max)
t
RC
(min)
t
RFC
(min)
t
CDL
(min)
t
RDL
(min)
t
BDL
(min)
t
CCD
(min)
t
MRD
(min)
t
REF
(max)
CAS Latency=3
CAS Latency=2
55
Version
-5
10
15
15
40
-6
12
18
18
42
100
60
80
1
2
1
1
2
64
2
1
63
-7
14
21
21
42
Unit
ns
ns
ns
ns
us
ns
ns
CLK
CLK
CLK
CLK
CLK
ms
ea
Note
1
1
1
1
-
1
1,5
2
2
2
3
-
6
4
Last data in to new col. Address delay
Last data in to row precharge
Last data in to burst stop
Col. Address to col. Address delay
Mode Register command to Active or Refresh
Command
Refresh period(4,096 rows)
Number of valid output data
Note:
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
3. Minimum delay is required to complete write.
4. All parts allow every cycle column address change.
5. In case of row precharge interrupt, auto precharge and read burst stop.
The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks
5. A new command may be given t
RFC
after self refresh exit.
6. A maximum of eight consecutive AUTO REFRESH commands (with t
RFCmin
) can be posted to any given SDRAM, and
the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is
8x15.6μs.)
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2012
Revision: 1.0
5/47
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