ESMT
SDRAM
(Preliminary)
M12L128324A (2E)
1M x 32 Bit x 4 Banks
Synchronous DRAM
FEATURES
ORDERING INFORMATION
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
- CAS Latency (2 & 3)
- Burst Length (1, 2, 4, 8 & full page)
- Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the
system clock
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle)
Product ID
M12L128324A-5BG2E
M12L128324A-6BG2E
M12L128324A-7BG2E
Max
Freq.
200MHz
166MHz
143MHz
Package
90 FBGA
90 FBGA
90 FBGA
Comments
Pb-free
Pb-free
Pb-free
GENERAL DESCRIPTION
The M12L128324A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 32 bits.
Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system applications.
BALL CONFIGURATION (TOP VIEW)
(BGA90, 8mmX13mmX1.4mm Body, 0.8mm Ball Pitch)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2
3
4
5
6
7
VDD
8
9
DQ26 DQ24 VSS
DQ28 VDDQ VSSQ
VSSQ DQ27 DQ25
VSSQ DQ29 DQ30
VDDQ DQ31
VSS DQM3
A4
A7
CLK
DQM1
A5
A8
CKE
NC
NC
A3
A6
NC
A9
NC
VSS
DQ23 DQ21
VDDQ VSSQ DQ19
DQ22 DQ20 VDDQ
DQ17 DQ18 VDDQ
NC
A2
A10/AP
NC
BA0
CAS
VDD
DQ6
DQ1
DQ16 VSSQ
DQM2 VDD
A0
BA1
CS
WE
A1
A11
RAS
DQM0
VDDQ DQ8
DQ7 VSSQ
DQ5 VDDQ
DQ3 VDDQ
VSSQ DQ10 DQ9
VSSQ DQ12 DQ14
DQ11 VDDQ VSSQ
DQ13 DQ15 VSS
VDDQ VSSQ DQ4
VDD
DQ0
DQ2
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2011
Revision: 0.1
1/44
ESMT
BLOCK DIAGRAM
CLK
CKE
Address
Mode
Register
Clock
Generator
(Preliminary)
M12L128324A (2E)
Bank D
Bank C
Bank B
Row
Address
Buffer
&
Refresh
Counter
Row Decoder
Bank A
Sense Amplifier
Command Decoder
Control Logic
CS
RAS
CAS
WE
Data Control Circuit
Input & Output
Buffer
Latch Circuit
Column
Address
Buffer
&
Refresh
Counter
DQM0~3
Column Decoder
DQ
PIN DESCRIPTION
PIN
CLK
CS
CKE
A0 ~ A11
BA0 , BA1
RAS
NAME
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
INPUT FUNCTION
Active on the positive going edge to sample all inputs
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM0-3.
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior new command.
Disable input buffers for power down in standby.
Row / column address are multiplexed on the same pins.
Row address : RA0~RA11, column address : CA0~CA7
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column address on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS ,
WE
active.
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when DQM active.
Data inputs / outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved
noise immunity.
This pin is recommended to be left No Connection on the device.
CAS
WE
Column Address
Strobe
Write Enable
Data Input / Output
Mask
Data Input / Output
Power Supply /
Ground
Data Output Power /
Ground
No Connection
DQM0~3
DQ0 ~ DQ31
V
DD
/ V
SS
V
DDQ
/ V
SSQ
NC
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2011
Revision: 0.1
2/44
ESMT
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to V
SS
Voltage on V
DD
supply relative to V
SS
Storage temperature
Power dissipation
Short circuit current
Note:
(Preliminary)
M12L128324A (2E)
Symbol
V
IN
, V
OUT
V
DD
, V
DDQ
T
STG
P
D
I
OS
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
1
50
Unit
V
V
°
C
W
mA
Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITION
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= 0 to 70 °C )
Parameter
Supply voltage
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Output leakage current
Note:
Symbol
V
DD
, V
DDQ
V
IH
V
IL
V
OH
V
OL
I
IL
I
OL
Min
3.0
2.0
-0.3
2.4
-
-5
-5
Typ
3.3
3.0
0
-
-
-
-
Max
3.6
V
DD
+0.3
0.8
-
0.4
5
5
Unit
V
V
V
V
V
1
2
I
OH
= -2mA
I
OL
= 2mA
3
4
Note
μ
A
μ
A
1. V
IH
(max) = 4.6V AC for pulse width
≤
10ns acceptable.
2. V
IL
(min) = -1.5V AC for pulse width
≤
10ns acceptable.
3. Any input 0V
≤
V
IN
≤
V
DD
, all other pins are not under test = 0V.
4. Dout is disabled, 0V
≤
V
OUT
≤
V
DD
.
CAPACITANCE
(V
DD
= 3.3V, T
A
= 25 °C , f = 1MHz)
Parameter
Input capacitance (A0 ~ A11, BA0 ~ BA1)
Input capacitance
(CLK, CKE, CS , RAS , CAS ,
WE
& DQM)
Data input/output capacitance (DQ0 ~ DQ31)
Symbol
CIN1
CIN2
COUT
Min
2
2
2
Max
4
4
5
Unit
pF
pF
pF
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2011
Revision: 0.1
3/44
ESMT
DC CHARACTERISTICS
(Preliminary)
M12L128324A (2E)
Recommended operating condition unless otherwise noted，T
A
= 0 to 70 °C
Test Condition
-5
Burst Length = 1
I
CC1
t
RC
≥
t
RC
(min)
I
OL
= 0 mA
CKE
≤
V
IL
(max), t
CC
= 10ns
CKE & CLK
≤
V
IL
(max), t
CC
=
∞
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
input signals are stable
CKE
≤
V
IL
(max), t
CC
= 10ns
CKE & CLK
≤
V
IL
(max), t
CC
=
∞
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
=15ns
Input signals are changed one time during 2clks
All other pins
≥
VDD-0.2V or
≤
0.2V
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
input signals are stable
I
OL
= 0 mA
Page Burst
2 Banks activated
t
CC
= t
CC
(min)
t
RFC
≥
t
RFC
(min)
CKE
≤
0.2V
140
120
100
mA
1,2
Version
-6
-7
Unit Note
Parameter
Operating Current
(One Bank Active)
Symbol
Precharge Standby Current I
CC2P
in power-down mode
I
CC2PS
Precharge Standby Current
in non power-down mode
I
CC2N
I
CC2NS
Active Standby Current
in power-down mode
I
CC3P
I
CC3PS
I
CC3N
I
CC3NS
2.5
2
25
mA
mA
18
20
20
35
25
mA
Active Standby Current
in non power-down mode
(One Bank Active)
mA
mA
Operating Current
(Burst Mode)
Refresh Current
Self Refresh Current
Note:
I
CC4
I
CC5
I
CC6
290
290
270
270
4
240
240
mA
mA
mA
1,2
1. Measured with outputs open.
2. Input signals are changed one time during 2 CLKS.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2011
Revision: 0.1
4/44
ESMT
Parameter
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall-time
Output timing measurement reference level
Output load condition
(Preliminary)
M12L128324A (2E)
Unit
V
V
ns
V
AC OPERATING TEST CONDITIONS
(V
DD
= 3.3V
±
0.3V
，T
A
= 0 to 70 °C )
Value
2.4/0.4
1.4
tr/tf = 1/1
1.4
See Fig. 2
Vtt = 1.4V
3.3V
1200
Output
870
Ω
30pF
Ω
V
OH
(DC) =2.4V , I
OH
= -2 mA
V
OL
(DC) =0.4V , I
OL
= 2 mA
Output
Z0 =50
50
Ω
Ω
30pF
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
@ Operating
@ Auto Refresh
Symbol
t
RRD
(min)
t
RCD
(min)
t
RP
(min)
t
RAS
(min)
t
RAS
(max)
t
RC
(min)
t
RFC
(min)
t
CDL
(min)
t
RDL
(min)
t
BDL
(min)
t
CCD
(min)
60
60
-5
10
15
15
40
-6
12
18
18
42
100
60
60
1
2
1
1
2
ea
CAS latency = 2
1
4
63
63
-7
14
21
21
42
Unit
ns
ns
ns
ns
us
ns
CLK
CLK
CLK
CLK
1
1, 5
2
2
2
3
Note
1
1
1
1
Last data in to col. address delay
Last data in to row precharge
Last data in to burst stop
Col. address to col. address delay
Number of valid
Output data
CAS latency = 3
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. A new command may be given t
RFC
after self refresh exit.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2011
Revision: 0.1
5/44
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