ESMT
SDRAM
M12L128168A (2N)
Automotive Grade
2M x 16 Bit x 4 Banks
Synchronous DRAM
FEATURES
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
- CAS Latency ( 2 & 3 )
- Burst Length ( 1, 2, 4, 8 & full page )
- Burst Type ( Sequential & Interleave )
All inputs are sampled at the positive going edge of the
system clock
Burst Read single write operation
DQM for masking
Auto & self refresh
(self refresh is not supported for VA grade)
Refresh
- 64ms refresh period (4K cycle) for V grade
- 16ms refresh period (4K cycle) for VA grade
GENERAL DESCRIPTION
The M12L128168A is 134,217,728 bits synchronous high
data rate Dynamic RAM organized as 4 x 2,097,152 words
by 16 bits. Synchronous design allows precise cycle control
with the use of system clock I/O transactions are possible on
every clock cycle. Range of operating frequencies,
programmable burst length and programmable latencies
allow the same device to be useful for a variety of high
bandwidth, high performance memory system applications.
ORDERING INFORMATION
Product ID
M12L128168A-5TVG2N
M12L128168A-5BVG2N
M12L128168A-6TVG2N
M12L128168A-6BVG2N
M12L128168A-7TVG2N
M12L128168A-7BVG2N
Max Freq.
200MHz
200MHz
166MHz
166MHz
143MHz
143MHz
Package
54 Pin TSOPII
54 Ball FBGA
54 Pin TSOPII
54 Ball FBGA
54 Pin TSOPII
54 Ball FBGA
Comments
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Automotive range (V): -40℃ to +85℃
Automotive range (VA): -40℃ to +105℃
M12L128168A-5TVAG2N
M12L128168A-5BVAG2N
M12L128168A-6TVAG2N
M12L128168A-6BVAG2N
M12L128168A-7TVAG2N
M12L128168A-7BVAG2N
200MHz
200MHz
166MHz
166MHz
143MHz
143MHz
54 Pin TSOPII
54 Ball FBGA
54 Pin TSOPII
54 Ball FBGA
54 Pin TSOPII
54 Ball FBGA
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.1
1/46
ESMT
BLOCK DIAGRAM
CLK
CKE
Address
Mode
Register
Clock
Generator
M12L128168A (2N)
Automotive Grade
Bank D
Bank C
Bank B
Row
Address
Buffer
&
Refresh
Counter
Row Decoder
Bank A
Sense Amplifier
Command Decoder
Control Logic
L(U)DQM
CS
RAS
CAS
WE
Column
Address
Buffer
&
Counter
Column Decoder
Input & Output
Buffer
Latch Circuit
Data Control Circuit
DQ
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.1
2/46
ESMT
PIN CONFIGURATION (TOP VIEW)
(TSOPII 54L, 400milX875mil Body, 0.8mm Pin Pitch)
M12L128168A (2N)
Automotive Grade
BALL CONFIGURATION (TOP VIEW)
(BGA 54, 8mmX8mmX1mm Body, 0.8mm Ball Pitch)
PIN DESCRIPTION
PIN
CLK
CS
CKE
A0 ~ A11
BA0 , BA1
RAS
CAS
WE
NAME
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input / Output Mask
Data Input / Output
Power Supply / Ground
Data Output Power / Ground
No Connection
INPUT FUNCTION
Active on the positive going edge to sample all inputs
Disables or enables device operation by masking or enabling all
inputs except CLK , CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior new command.
Disable input buffers for power down in standby.
Row / column address are multiplexed on the same pins.
Row address : RA0~RA11, column address : CA0~CA8
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
Latches row addresses on the positive going edge of the CLK with
RAS low. (Enables row access & precharge.)
Latches column address on the positive going edge of the CLK with
CAS low. (Enables column access.)
Enables write operation and row precharge.
Latches data in starting from CAS ,
WE
active.
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when L(U)DQM active.
Data inputs / outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
This pin is recommended to be left No Connection on the device.
L(U)DQM
DQ0 ~ DQ15
V
DD
/ V
SS
V
DDQ
/ V
SSQ
NC
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.1
3/46
ESMT
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to V
SS
Voltage on V
DD
supply relative to V
SS
Operating ambient temperature
Storage temperature
Power dissipation
Short circuit current
Note:
Symbol
V
IN
, V
OUT
V
DD
, V
DDQ
T
A
(V grade)
T
A
(VA grade)
TSTG
PD
I
OS
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-40 ~ +85
M12L128168A (2N)
Automotive Grade
Unit
V
V
°C
°C
°
C
W
mA
-40 ~ +105
-55 ~ +150
1
50
Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITION
Recommended operating conditions (Voltage referenced to V
SS
= 0V)
Parameter
Supply voltage
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Output leakage current
Note:
Symbol
V
DD
, V
DDQ
V
IH
V
IL
V
OH
V
OL
I
IL
I
OL
Min
3.0
2.0
-0.3
2.4
-
-5
-5
Typ
3.3
3.0
0
-
-
-
-
Max
3.6
V
DD
+0.3
0.8
-
0.4
5
5
Unit
V
V
V
V
V
μ
A
Note
1
2
I
OH
= -2mA
I
OL
= 2mA
3
4
μ
A
1. V
IH
(max) = 4.6V AC for pulse width
≤
10ns acceptable.
2. V
IL
(min) = -1.5V AC for pulse width
≤
10ns acceptable.
3. Any input 0V
≤
V
IN
≤
V
DD
, all other pins are not under test = 0V.
4. Dout is disabled, 0V
≤
V
OUT
≤
V
DD.
CAPACITANCE
(V
DD
= 3.3V, T
A
= 25
°
C , f = 1MHz)
Parameter
Input capacitance (A0 ~ A11, BA0 ~ BA1)
Input capacitance (CLK, CKE, CS , RAS , CAS ,
WE
& L(U)DQM)
Symbol
C
IN1
C
IN2
C
OUT
Min
2
2
2
Max
5
5
5
Unit
pF
pF
pF
Data input/output capacitance (DQ0 ~ DQ15)
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.1
4/46
ESMT
DC CHARACTERISTICS
Recommended operating condition unless otherwise noted
Parameter
Operating Current
(One Bank Active)
Precharge Standby Current
in power-down mode
Symbol
Test Condition
M12L128168A (2N)
Automotive Grade
Version
-5
-6
100
2
2
20
-7
90
Unit
Note
I
CC1
I
CC2P
I
CC2PS
I
CC2N
I
CC2NS
Burst Length = 1, t
RC
≥
t
RC
(min), I
OL
= 0 mA
CKE
≤
V
IL
(max), t
CC
= t
CC
(min)
CKE & CLK
≤
V
IL
(max), t
CC
=
∞
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= t
CC
(min)
Input signals are changed one time during 2t
CC
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
input signals are stable
CKE
≤
V
IL
(max), t
CC
= t
CC
(min)
CKE & CLK
≤
V
IL
(max), t
CC
=
∞
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
=15ns
110
mA
mA
1,2
Precharge Standby Current
in non power-down mode
mA
10
5
5
mA
Active Standby Current
in power-down mode
I
CC3P
I
CC3PS
Active Standby Current
in non power-down mode
(One Bank Active)
I
CC3N
Input signals are changed one time during 2clks
All other pins
≥
V
DD
-0.2V or
≤
0.2V
25
mA
I
CC3NS
Operating Current
(Burst Mode)
Refresh Current
Self Refresh Current
Note:
I
CC4
I
CC5
I
CC6
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
input signals are stable
I
OL
= 0 mA, Page Burst, 4 Banks activated
t
RFC
≥
t
RFC
(min)
CKE
≤
0.2V
120
210
15
110
200
2
100
190
mA
mA
mA
mA
1,2
1. Measured with outputs open.
2. Input signals are changed one time during 2 CLKS.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.1
5/46
FPGA/CPLD
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