PJSR70
Low Capacitance Diode Array
This diode array is configured to protect up to two data transmission lines
acting as a line terminator, minimizing overshoot and undershoot conditions
due to bus impedance as well as protect against over-voltage events as
electrostatic discharges
3
4
DRAFT SPEC
2
SPECIFICATION FEATURES
Maximum Capacitance of 5.0pF at 0Vdc 1MHz Line-to-Ground
Maximum Leakage Current of 1µA @ VRWM
Industry Standard SMT Package SOT143
IEC61000-4-2 Full Compliance; 15kV Air, 8kV Contact
100% Tin Matte finish (LEAD-FREE PRODUCT)
VREF
4
I/O2
3
1
2
I/O1
1
GND
SOT143
APPLICATIONS
USB 2.0 and Firewire Port Protection
LAN/WLAN Access Point terminals
Video Signal line protection
I
2
C Bus Protection
MAXIMUM RATINGS
Tj = 25°C Unless otherwise noted
Rating
Peak Pulse Current (8/20µs Waveform)
Rectifier Repetitive Peak Reverse Voltage
Operating Junction Temperature Range
Storage Temperature Range
Soldering Temperature, t max = 10s
Symbol
I
PPM
V
RRM
T
J
T
stg
T
L
Value
24
70
-55 to +125
-55 to +150
260
Units
A
V
°C
°C
°C
12/5/2005
Page 1
www.panjit.com
PJSR70
ELECTRICAL CHARACTERISTICS
Parameter
Reverse Stand-Off Voltage
Symbol
V
RWM
V
BR
I
R
V
FC
V
FC
V
FC
Cj
I
BR
= 50µA
V
R
= 70V
I pp = 1A
I pp = 10A
I pp = 24A
0 Vdc Bias f = 1MHz
Between I/O pins and GND
0 Vdc Bias f = 1MHz
Between I/O pins
Tj = 25°C unless otherwise noted
Conditions
Min
Typical
Max
70
85
1
1.5
3.3
7
5
3
Units
V
V
µA
V
V
V
pF
pF
DRAFT SPEC
Reverse Breakdown Voltage
Reverse Leakage Current
Clamping Voltage (8/20µs)
Clamping Voltage (8/20µs)
Clamping Voltage (8/20µs)
Off State Junction Capacitance
12/5/2005
Page 2
www.panjit.com
FPGA/CPLD
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