EFST
preliminary
F49L004UA / F49L004BA
4 Mbit (512K x 8)
3V Only CMOS Flash Memory
1. FEATURES
Single supply voltage 2.7V-3.6V
!
Fast access time: 70/90 ns
!
Compatible with JEDEC standard
- Pinout, packages and software commands
compatible with single-power supply Flash
!
Low power consumption
- 20mA typical active current
- 0.2uA typical standby current
!
10,000 minimum program/erase cycles
!
Command register architecture
- Byte programming (9us typical)
- Sector Erase(sector structure: one 16 KB, two 8 KB,
one 32 KB, and seven 64 KB)
!
Auto Erase (chip & sector) and Auto Program
- Any combination of sectors can be erased
concurrently; Chip erase also provided.
- Automatically program and verify data at specified
address
!
Erase Suspend/Erase Resume
- Suspend or Resume erasing sectors to allow the
read/program in another sector
!
!
!
!
!
!
!
!
Ready/Busy (RY/
BY
)
- RY/
BY
output pin for detection of program or erase
operation completion
End of program or erase detection
- Data polling
- Toggle bits
Hardware reset
- Hardware pin(
RESET
) resets the internal state machine
to the read mode
Sector Protection /Unprotection
- Hardware Protect/Unprotect any combination of sectors
from a program or erase operation.
Low V
CC
Write inhibit is equal to or less than 2.0V
Boot Sector Architecture
- U = Upper Boot Sector
- B = Bottom Boot Sector
Packages available:
- 40-pin TSOPI
- 32-pin PLCC
2. ORDERING INFORMATION
Part No
F49L004UA-70T
F49L004UA-70N
F49L004BA-70T
F49L004BA-70N
Boot
Upper
Upper
Bottom
Bottom
Speed
70 ns
70 ns
70 ns
70 ns
Package
TSOPI
PLCC
TSOPI
PLCC
Part No
F49L004UA-90 T
F49L004UA-90N
F49L004BA-90T
F49L004BA-90N
Boot
Upper
Upper
Bottom
Bottom
Speed
90 ns
90 ns
90 ns
90 ns
Package
TSOPI
PLCC
TSOPI
PLCC
3. GENERAL DESCRIPTION
The F49L004UA/ F49L004BA is a 4 Megabit, 3V only
CMOS Flash memory device organized as 512K bytes of 8
bits. This device is packaged in standard 40-pin TSOP and
32-pin PLCC. It is designed to be programmed and erased
both in system and can in standard EPROM programmers.
With access times of 70 ns and 90 ns, the F49L004UA/
F49L004BA allows the operation of high-speed
microprocessors. The device has separate chip enable
CE
, write enable
WE
, and output enable
OE
controls.
EFST's memory devices reliably store memory data even
after 100,000 program and erase cycles.
The F49L004UA/ F49L004BA is entirely pin and
command set compatible with the JEDEC standard for 4
Megabit Flash memory devices. Commands are written to
the command register using standard microprocessor write
timings.
The F49L004UA/ F49L004BA features a sector erase
architecture. The device memory array is divided into one
16 Kbytes, two 8 Kbytes, one 32 Kbytes, and seven 64
Kbytes. Sectors can be erased individually or in groups
without affecting the data in other sectors. Multiple-sector
erase and whole chip erase capabilities provide the
flexibility to revise the data in the device.
The sector protect/unprotect feature disables both
program and erase operations in any combination of the
sectors of the memory. This can be achieved in-system or
via programming equipment.
A low V
CC
detector inhibits write operations on loss of
power. End of program or erase is detected by the
Ready/Busy status pin, Data Polling of DQ7, or by the
Toggle Bit I feature on DQ6. Once the program or erase
cycle has been successfully completed, the device
internally resets to the Read mode.
Elite Flash Storage Technology Inc.
Publication Date : Aug. 2003
Revision: 0.2
1/46
EFST
7.1 Device operation
preliminary
F49L004UA / F49L004BA
7. FUNCTIONAL DESCRIPTION
This section describes the requirements and use
of the device bus operations, which are initiated
through the internal command register. The
register is composed of latches that store the
command, address and data information needed
to execute the command. The contents of the
register serve as inputs to
machine. The state machine
function of the device.
F49L004BA features various
Table 3.
the internal state
outputs dictate the
The F49L004UA/
bus operations as
Table 3. F49L004UA/F49L004BA Operation Modes Selection
ADDRESS
DESCRIPTION
CE
OE WE
RESET
A18 A12
|
|
A13 A10
A9
A8
|
A7
X
AIN
AIN
X
X
A6
A5
|
A2
A1 A0
DQ0~DQ7
Reset(3)
Read
Write
Output Disable
Standby
Sector Protect(2)
Sector Unprotect(2)
Temporary sector unprotect
Auto-select
Notes:
X
L
L
L
V
CC
±
0.3V
L
L
X
X
L
H
H
X
H
H
X
X
H
L
H
X
L
L
X
L, Vss±
0.3V(4)
H
H
H
V
CC
±
0.3V
V
ID
V
ID
V
ID
See Table 4
SA
SA
X
X
X
X
High Z
Dout
DIN
High Z
High Z
L
H
X
X
H
H
L
L
DIN
DIN
DIN
X
X
AIN
1.
L= Logic Low = V
IL
, H= Logic High = V
IH
, X= Don't Care, SA= Sector Address, V
ID
=11.5V to 12.5V.
AIN= Address In, DIN = Data In, Dout = Data Out.
2. The sector protect and unprotect functions may also be implemented via programming equipment.
3.
RESET
pin for 40-TSOP package type only.
4. See “Reset Mode” section.
Elite Flash Storage Technology Inc.
Publication Date : Aug. 2003
Revision: 0.2
5/46
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