UTRON
Rev. 1.1
512K X 16 BITS LOW POWER PSEUDO SRAM
UT65L168(E)/UT65L168(I)
REVISION HISTORY
REVISION
Rev. 1.0
Rev. 1.1
DESCRIPTION
Original.
1. Delete Partial refresh function
2. Add Package : 48-pin 12mmX20mm TSOP-I
Draft Date
Apr. 15, 2003
Aug. 06,2003
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80094
1
UTRON
Rev. 1.1
512K X 16 BITS LOW POWER PSEUDO SRAM
GENERAL DESCRIPTION
UT65L168(E)/UT65L168(I)
The UT65L168 is a 8,388,608-bit CMOS random
access memory organized as 524,288 words by 16
bits. It is fabricated using PSEUDO SRAM techniques,
yields high-density and low power consumption
device.
The UT65L168 is design for upper and low byte
access by data byte control ( UB
、
LB
).It has low
power modes by using control pin
ZZ
.
FEATURES
Fast access time : 60/70ns (max.)
Low operating power
Operating current : 20mA (typ)
Standby current : 50uA (typ)
Power supply voltage : 2.5V~3.3V
Operating temperature :
Extended(E) : -20
℃
~ 80
℃
Industrial(I) : -40
℃
~ 85
℃
Low power modes
Deep power Down : Isb < 10uA
Three state output and TTL compatible
Separated I/O power (Vccq) & Core Power (Vcc)
Page mode operation by 8 words
Data byte control :
LB
(I/O1~I/O8)
UB (I/O9~I/O16)
Package : 48-pin 6.0mm × 8.0mm TFBGA
48-pin 12mmX20mm TSOP-I
PIN DESCRIPTION
SYMBOL
A0 - A18
I/O1 - I/O16
CE
WE
OE
LB
UB
ZZ
V
CC
Vccq
V
SS
NC
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip enable Input
Write Enable Input
Output Enable Input
Lower Byte Control
Upper Byte Control
Low Power Modes
Core Power
I/O power
Ground
No Connection
FUNCTIONAL BLOCK DIAGRAM
A0-A18
Vcc
Vccq
Vss
I/O1-I/O8
Lower Byte
I/O9-I/O16
Upper Byte
DECODER
512K
×
16
MEMORY
ARRAY
I/O DATA
CIRCUIT
PIN CONFIGURATION
COLUMN I/O
A
CE
LB
I/O9
I/O10
OE
UB
I/O11
I/O12
I/O13
A0
A3
A5
A17
Vss
A14
A12
A9
A1
A4
A6
A7
A16
A15
A13
A10
A2
CE
I/O2
I/O4
I/O5
I/O6
WE
A11
ZZ
I/O1
I/O3
Vcc
Vss
I/O7
I/O8
NC
B
OE
WE
LB
UB
ZZ
CONTROL
CIRCUIT
C
D
E
F
G
H
Vss
Vccq
I/O15
I/O16
I/O14
NC
A8
A18
1
2
3
4
5
6
TFBGA
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80094
2
UTRON
Rev. 1.1
512K X 16 BITS LOW POWER PSEUDO SRAM
UT65L168(E)/UT65L168(I)
PIN CONFIGURATION
A13
A14
A15
A16
A17
A18
A1
A0
NC
NC
WE
ZZb
NC
UB
LB
A10
A9
A8
A7
A6
A5
A4
A3
A2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A12
NC
Vss
I/O16
I/O8
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
Vcc
I/O12
I/O4
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
OE
Vss
CE
A11
UT65L168
TSOP-I
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Voltage on any pin relative to V
SS
Voltage on Vcc supply relative to V
SS
Extended
Operating Temperature
Industrial
Storage Temperature
Power Dissipation
SYMBOL
V
IN
, V
OUT
V
CC
T
A
T
A
T
STG
P
D
RATING
-0.2 to Vcc+0.3
-0.2 to 4.2
-25 to 80
-40 to 85
-65 to +150
1.0
UNIT
V
V
℃
℃
℃
W
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE
Standby
Output Disable
Read
CE
OE
X
H
H
L
L
L
X
X
X
X
WE
LB
UB
X
X
L
H
L
L
H
L
L
X
ZZ
I/O OPERATION
SUPPLY CURRENT
I/O1-I/O8 I/O9-I/O16
High – Z
High – Z
D
OUT
High – Z
D
OUT
D
IN
High – Z
D
IN
High – Z
High – Z
High – Z
High – Z
D
OUT
D
OUT
High – Z
D
IN
D
IN
High – Z
I
SB
, I
SB1
I
CC
,I
CC1
,I
CC2
I
CC
,I
CC1
,I
CC2
I
CC
,I
CC1
,I
CC2
I
SB0
H
L
L
L
L
L
L
L
L
X
X
H
H
H
H
H
L
L
L
X
X
L
X
L
H
L
L
H
L
X
H
H
H
H
H
H
H
H
H
L
Write
Deep Power Down
Note:
H = V
IH
, L=V
IL
, X = Don't care.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80094
3
UTRON
Rev. 1.1
512K X 16 BITS LOW POWER PSEUDO SRAM
UT65L168(E)/UT65L168(I)
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.5V~3.3V)
PARAMETER
Power Voltage
I/O operating voltage
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
SYMBOL
V
CC
Vccq
V
IH
*2*3
V
IL
I
LI
I
LO
V
OH
V
OL
Icc
Average Operating
Current
*1*3
TEST CONDITION
MIN.
2.5
2.5
2.2
-0.2
-1
-1
2.2
-
-
TYP.
3.0
3.0
-
-
-
-
2.7
-
20
MAX.
3.3
3.3
V
CC
+0.2
0.4
1
1
-
0.4
30
UNIT
V
V
V
V
µA
µA
V
V
mA
V
SS
≦
V
IN
≦
V
CC
V
SS
≦
V
I/O
≦
V
CC;
Output Disable
I
OH
= -1mA
I
OL
= 2mA
Cycle time=Min,100%duty, I
I/O
=0mA
CE
=V
IL
,
ZZ
= V
IH
, V
IN
=V
IL
or V
IH
Cycle time=1µs,100%duty, I
I/O
=0mA
Icc1
I
SB
I
SB1
I
SB0
CE
≦
0.2V,
ZZ
= V
IH
V
IN
≦
0.2V or V
IN
≧
Vcc-0.2V
-
-
-
-
-
-
50
-
7
0.3
70
10
mA
mA
µA
µA
Standby Current (TTL)
Standby Current (CMOS)
Deep Power Down
CE
=
ZZ
=V
IH,
other inputs =V
IL
or V
IH
CE
≧
Vcc-0.2 ,
ZZ
≧
Vcc-0.2V
other inputs = 0 ~ Vcc
No refresh
LL
ZZ
≦
0.2V, other pins = 0 ~ Vcc LL
Note :
*1.Overshoot : Vcc+1.0V in case of pulse width
≦
20ns.
*2.Undershoot : -1.0V in case of pulse width
≦
20ns.
*3.Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE
(T
A
=25
℃
, f=1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
C
IN
C
I/O
MIN.
-
-
MAX
8
8
UNIT
pF
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80094
4
UTRON
Rev. 1.1
512K X 16 BITS LOW POWER PSEUDO SRAM
UT65L168(E)/UT65L168(I)
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0.2V to 2.4V
5ns
1.5V
C
L
= 30pF+1TTL, I
OH
/I
OL
= -1mA / 2mA
AC ELECTRICAL CHARACTERISTICS
(V
CC
=2.5V~3.3V)
(1) READ CYCLE
PARAMETER
Read Cycle Time
Address Access Time
Chip enable to output
Output Enable to Valid Output
Chip enable to Low-Z output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
LB
,
UB
Access Time
LB
,
UB
LB
,
UB
SYMBOL
t
RC
t
AA
t
ACE
t
OE
t
CLZ
t
OLZ
t
CHZ
t
OHZ
t
OH
t
BA
t
BHZ
t
BLZ
Disable
to High-Z Output
Enable
to Low-Z Output
UT65L168-60
MIN.
MAX.
60
40k
-
60
-
60
-
25
10
-
5
-
0
5
0
5
5
-
-
60
0
5
10
-
UT65L168-70
MIN.
MAX.
70
40k
-
70
-
70
-
25
10
-
5
-
0
5
0
5
5
-
-
70
0
5
10
-
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(2) WRITE CYCLE
PARAMETER
Write Cycle Time
Address Valid to End of Write
Chip enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
Write to Output High Z
LB
,
UB
Valid to End of Write
SYMBOL
t
WC
t
AW
t
CW
t
AS
t
WP
t
WR
t
DW
t
DH
t
OW
t
WHZ
t
BW
UT65L168-60
MIN.
MAX.
60
40k
50
-
50
-
0
-
50
-
0
-
20
-
0
-
5
-
0
5
50
-
UT65L168-70
MIN.
MAX.
70
40k
60
-
60
-
0
-
50
-
0
-
20
-
0
-
5
-
0
5
60
-
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(3) PAGE MODE CYCLE
PARAMETER
Page Mode Cycle Time
Page Mode Address Access Time
Maximum Cycle Time
SYMBOL
t
PC
t
PAA
t
MRC
UT65L168-60
MIN.
MAX.
25
-
-
25
-
40k
UT65L168-70
MIN.
MAX.
25
-
-
25
-
40k
UNIT
ns
ns
ns
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80094
5
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