DDR3L
SODIMM
VR7PUxx6498xxx
MODULE CONFIGURATIONS
Viking Part Number
VR7PU286498FBZ
VR7PU286498FBA
VR7PU286498FBD
VR7PU286498FBx
VR7PU286498FBF
VR7PU566498FBZ
VR7PU566498FBA
VR7PU566498FBD
VR7PU566498FBx
VR7PU566498FBF
VR7PU566498GBZ
VR7PU566498GBA
VR7PU566498GBD
VR7PU566498GBx
VR7PU566498GBF
VR7PU126498GBZ
VR7PU126498GBA
VR7PU126498GBD
VR7PU126498GBx
VR7PU126498GBF
VR7PU126498HBZ
VR7PU126498HBA
VR7PU126498HBD
VR7PU126498HBx
VR7PU126498HBF
VR7PU1G6498HBZ
VR7PU1G6498HBA
VR7PU1G6498HBD
VR7PU1G6498HBx
VR7PU1G6498HBF
Capacity
1GB
1GB
1GB
1GB
1GB
2GB
2GB
2GB
2GB
2GB
2GB
2GB
2GB
2GB
2GB
4GB
4GB
4GB
4GB
4GB
4GB
4GB
4GB
4GB
4GB
8GB
8GB
8GB
8GB
8GB
Module
Configuration
128MX64
128MX64
128MX64
128MX64
128MX64
256MX64
256MX64
256MX64
256MX64
256MX64
256MX64
256MX64
256MX64
256MX64
256MX64
512MX64
512MX64
512MX64
512MX64
512MX64
512MX64
512MX64
512MX64
512MX64
512MX64
1GX64
1GX64
1GX64
1GX64
1GX64
Device
Configuration
128Mx8
128Mx8
128Mx8
128Mx8
128Mx8
128Mx8
128Mx8
128Mx8
128Mx8
128Mx8
256Mx8
256Mx8
256Mx8
256Mx8
256Mx8
256Mx8
256Mx8
256Mx8
256Mx8
256Mx8
512Mx8
512Mx8
512Mx8
512Mx8
512Mx8
512Mx8
512Mx8
512Mx8
512Mx8
512Mx8
Device
Package
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
Module
Ranks
1
1
1
1
1
2
2
2
2
2
1
1
1
1
1
2
2
2
2
2
1
1
1
1
1
2
2
2
2
2
Performance
PC3-6400
PC3-8500
PC3-10600
PC3-12800
PC3-12800
PC3-6400
PC3-8500
PC3-10600
PC3-12800
PC3-12800
PC3-6400
PC3-8500
PC3-10600
PC3-12800
PC3-12800
PC3-6400
PC3-8500
PC3-10600
PC3-12800
PC3-12800
PC3-6400
PC3-8500
PC3-10600
PC3-12800
PC3-12800
PC3-6400
PC3-8500
PC3-10600
PC3-12800
PC3-12800
CAS Latency
CL6 (6-6-6)
CL7 (7-7-7)
CL9 (9-9-9)
CL10 (10-10-10)
CL11 (11-11-11)
CL6 (6-6-6)
CL7 (7-7-7)
CL9 (9-9-9)
CL10 (10-10-10)
CL11 (11-11-11)
CL6 (6-6-6)
CL7 (7-7-7)
CL9 (9-9-9)
CL10 (10-10-10)
CL11 (11-11-11)
CL6 (6-6-6)
CL7 (7-7-7)
CL9 (9-9-9)
CL10 (10-10-10))
CL11 (11-11-11)
CL6 (6-6-6)
CL7 (7-7-7)
CL9 (9-9-9)
CL10 (10-10-10)
CL11 (11-11-11)
CL6 (6-6-6)
CL7 (7-7-7)
CL9 (9-9-9)
CL10 (10-10-10)
CL11 (11-11-11)
Note:
For part numbers containing an x, contact Viking for the complete PN
Features
•
JEDEC standard Power Supply
o
VDD = 1.35V (1.283V to 1.45V)
o
VDDSPD = +3.0V to +3.6V
o
Backward Compatible with 1.5V DDR3 DIMMs
VDD = 1.5V (1.425V to 1.575V)
204pin Small Outline Dual-In-Line Memory Module.
8 Internal Banks.
Programmable CAS Latency: 6, 7, 8, 9, 10, 11
Programmable CAS Write Latency (CWL).
Programmable Additive Latency (Posted CAS).
•
•
•
•
•
•
•
Fixed burst chop (BC) of 4 and burst length (BL) of 8 via
the mode register set (MRS)
Selectable BC4 or BL8 on-the-fly (OTF)
On-Die-Termination (ODT) and Dynamic ODT for improved
signal integrity.
Refresh. Self Refresh and Power Down Modes.
Serial Presence Detect with EEPROM.
On-DIMM Thermal Sensor.
RoHS Compliant* (see last page)
•
•
•
•
•
Viking Technology♦20091 Ellipse♦Foothill Ranch, CA 92610
Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.Vikingtechnology.com
This Data Sheet is subject to change without notice.
Doc. # PS7PUxx6498xxx-LF
Revision B
Page 1 of 27
DDR3L
SODIMM
VR7PUxx6498xxx
PIN FUNCTION DESCRIPTION
SYMBOL
CK0, CK1
CK0#, CK1#
TYPE
IN
IN
POLARITY
Positive Edge
Negative Edge
DESCRIPTION
Positive lines of the differential pairs of system clock inputs. All control, command, and
address input signals are sampled on the crossing of the positive edge of CK and the
negative edge of CK#.
Negative lines of the differential pairs of system clock inputs. All control, command, and
address input signals are sampled on the crossing of the positive edge of CK and the
negative edge of CK#.
CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input
buffers and output drivers of the SDRAMs. Taking CKE LOW provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER
DOWN (row ACTIVE in any bank)
Enables the associated SDRAM command decoder when low and disables decoder when
high. When decoder is disabled, new commands are ignored and previous operations
continue
On-Die Termination control signals
When sampled at the positive rising edge of the clock, CAS#, RAS#, and WE# define the
operation to be executed by the SDRAM.
Reference voltage for DQ0-DQ63 and CB0-CB7.
Reference voltage for A0-A15, BA0-BA2, RAS#, CAS#, WE#, S0#, S1#, CKE0, CKE1,
Par_In, ODT0 and ODT1.
Selects which SDRAM bank of eight is activated. BA0 - BA2 define to which bank an
Active, Read, Write or Precharge command is being applied. Bank address also
determines mode register is to be accessed during an MRS cycle.
Provided the row address for Active commands and the column address
and Auto Precharge bit for Read/Write commands to select one location out of the
memory array in the respective bank. A10 is sampled during a Precharge command to
determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10
HIGH). If only one bank is to be precharged, the bank is selected by BA. A12 is also
utilized for BL 4/8 identification for ‘’BL on the fly’’ during CAS# command. The address
inputs also provide the op-code during Mode Register Set commands.
Data and Check Bit Input/Output pins
Power and ground for the DDR SDRAM input buffers and core logic.
Masks write data when high, issued concurrently with input data.
Power and ground for the DDR SDRAM input buffers and core logic.
Termination Voltage for Address/Command/Control/Clock nets.
Positive line of the differential data strobe for input and output data.
Negative line of the differential data strobe for input and output data.
These signals are tied at the system planar to either VSS or VDDSPD to configure the
serial SPD EEPROM address range.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to V
DDSPD
on the system planar to act as a
pullup.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from the SCL bus time to VDDSPD on the system planar to act as a pullup.
This signal indicates that a thermal event has been detected in the thermal sensing
device.The system should guarantee the electrical level requirement is met for the
EVENT pin on TS/SPD part.
Serial EEPROM positive power supply wired to a separate power pin at the connector
which supports from 3.0 Volt to 3.6 Volt (nominal 3.3V) operation.
This signal resets the DDR3 SDRAM.
CKE[1:0]
IN
Active High
S[1:0]#
ODT[1:0]
RAS#, CAS#,
WE#
VREFDQ
VREFCA
BA[2:0]
IN
IN
IN
Supply
Supply
IN
Active Low
Active High
Active Low
-
A[15:13,
12/BC,11,
10/AP,9:0]
DQ [63:0],
VDD, VSS
DM [7:0]
VDD, VSS
VTT
DQS[7:0]
DQS [7:0]#
SA [1:0]
SDA
SCL
EVENT#
VDDSPD
RESET#
IN
-
I/O
Supply
IN
Supply
Supply
I/O
I/O
IN
I/O
IN
OUT
(open drain)
Supply
IN
-
-
Active High
Positive Edge
Negative Edge
-
-
-
Active Low
-
Viking Technology♦20091 Ellipse♦Foothill Ranch, CA 92610
Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.Vikingtechnology.com
This Data Sheet is subject to change without notice.
Doc. # PS7PUxx6498xxx-LF
Revision B
Page 4 of 27
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