PJQMF05LC
5-TVS/ZENER ARRAY FOR ESD AND LATCH-UP PROTECTION
This 5-TVS/Zener Array has been designed to Protect Sensitive Equipment
against ESD and to prevent Latch-Up events in CMOS circuitry
operating at 5Vdc and below. This TVS array offers an integrated solution to
protect up to 5 data lines where the board space is a premium.
6
5
4
PRELIMINARY
SPECIFICATION FEATURES
100W Power Dissipation (8x20µsec Waveform)
Low Leakage Current, Maximum of 2µA @ 5Vdc
Very Low Clamping Voltage, Max of 10V @ 9Apk 8x20µsec
IEC61000-4-2 ESD 20kV air, 15kV Contact Compliance
Max off state Capacitance of 90pF @ 0Vdc 1 MHz
New SMT package QFN 1.6mm x 1.6mm; Max Height of 0.75mm
Same Footprint compared to the SOT563
1
2
3
6
5
4
1
2
3
APPLICATIONS
Personal Digital Assistant (PDA)
SIM Card Port Protection (Mobile Phone)
Portable Instrumentation
Mobile Phones and Accessories
Memory Card Port Protection
1
3
2
QFN 2X2
6
5
4
QFN 1.6x1.6 sq mm Package
MAXIMUM RATINGS (Per Device)
Rating
Peak Pulse Power (8x20µsec Waveform)
Peak Pulse Current (8x20µsec Waveform)
ESD Voltage (HBM)
Operating Temperature Range
Storage Temperature Range
Symbol
P
pp
I
pp
V
ESD
TJ
T
stg
Value
100
10
>25
-55 to +125
-55 to + 150
Units
W
A
kV
°C
°C
ELECTRICAL CHARACTERISTICS (Per Device)
Tj = 25°C
Parameter
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamping Voltage (8x20µsec)
Clamping Voltage (8x20µsec)
Off State Junction Capacitance
Off State Junction Capacitance
Symbol
V
WRM
V
BR
I
R
V
cl
V
cl
Cj
Cj
I
BR
= 1 mA
V
R
= 5V
I pp = 5A
I pp = 9A
0 Vdc Bias f = 1MHz
Between I/O pins and pin 2
5 Vdc Bias f = 1MHz
Between I/O pins and pin 2
Conditions
Min
Typical
Max
5
Units
V
V
µA
V
V
pF
pF
6
7.2
2.0
9
10
90
45
1/26/2004
Page
1
www.panjit.com
PJQMF05LC
TYPICAL CHARACTERISTICS
25°C unless otherwise noted
Capacitance, pF
Ipp, Amps
PRELIMINARY
Non-Repetitive Peak Pulse Power vs Pulse Time
1000
Peak Pulse Power - Ppp (W)
Pulse Waveform
110
100
90
80
70
60
50
40
30
20
10
0
0
100
Percent of Ipp
50% of Ipp @ 20µs
R tim 10-90% - 8µs
ise e
10
1
10
100
1000
Pulse Duration, µsec
5
10
15
20
25
30
time, µsec
Capacitance vs. Biasing Voltage @1MHz
Clamping Voltage vs Ipp 8x20µsec Surge
100
10
9
8
7
6
5
4
3
2
1
0
6
7
8
9
10
11
Clamping Voltage, V
90
80
70
60
50
40
30
0
1
2
3
4
5
Bias Voltage, Vdc
1/26/2004
Page 2
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