Chrontel
◊
CH7317A
CH7317A SDVO / RGB DAC
Features
•
•
•
•
•
•
•
•
•
•
◊
High-speed SDVO (1G~2Gbps) AC-coupled serial
differential RGB inputs
Support for VGA RGB bypass
Output Analog RGB.
Three 10-bit video DAC outputs
DAC output CRT RGB connector
Fully programmable through serial port
Programmable power management
Configuration through Intel
®
SDVO OpCode
◊
Complete Windows driver support
Offered in 64-pin LQFP and 64-pin QFN package
Intel
®
Proprietary.
◊
General Description
The CH7317A is a Display Controller device which accepts
a digital graphics high speed AC coupled serial differential
RGB input signal, and encodes and transmits data through
analog RGB port. The device accepts one channel of RGB
data over three pairs of serial data ports.
CH7317A output VGA style analog RGB for use as a CRT
DAC. Supported analog video VGA connector.
XI/FIN,XO
2
PLL
Serial
Port
Control
AS
SPC
SPD
RESET*
BCO/VSYNC
C/HSYNC
Control
SC_DDC
SD_DDC
SC_PROM
SD_PROM
SDVO_Clk(+,-)
2
Clock
Driver
DAC 2
DAC 1
3
DACA[2:0]
10bit-8bit
decoder
SDVO_R(+,-)
SDVO_G(+,-)
SDVO_B(+,-)
DAC 0
Three
10-bit DAC's
6
ISET
Data Latch,
Serial to Parallel
Figure 1: Functional Block Diagram
201-0000-087
Rev. 1.2,
12/2/2008
1
CHRONTEL
Table of Contents
1.0
1.1
1.2
CH7317A
Pin-Out ____________________________________________________________________ 4
Package Diagram ___________________________________________________________________4
Pin Description _____________________________________________________________________6
2.0
2.1
2.2
2.3
2.4
Functional Description________________________________________________________ 8
Input Interface______________________________________________________________________8
CRT Bypass Operation _______________________________________________________________8
Command Interface _________________________________________________________________9
Boundary scan Test__________________________________________________________________9
3.0
4.0
4.1
4.2
4.3
4.4
4.5
Register Control ____________________________________________________________ 12
Electrical Specifications ______________________________________________________ 13
Absolute Maximum Ratings __________________________________________________________13
Recommended Operating Conditions ___________________________________________________13
Electrical Characteristics ____________________________________________________________14
DC Specifications __________________________________________________________________14
AC Specifications __________________________________________________________________16
5.0
6.0
Package Dimensions _________________________________________________________ 18
Revision History ____________________________________________________________ 20
2
201-0000-087
Rev. 1.2,
12/2/2008
CHRONTEL
Figures and Tables
List of Figures
CH7317A
Figure 1: Functional Block Diagram .............................................................................................................................1
Figure 2: 64-Pin LQFP Package ....................................................................................................................................4
Figure 3: 64-Pin QFN Package......................................................................................................................................5
Figure 4: Control Bus Switch ........................................................................................................................................9
Figure 5: NAND Tree Connection...............................................................................................................................10
Figure 6: 64 Pin LQFP Package ..................................................................................................................................18
Figure 7: 64 Pin QFN Package (8 x 8 x 0.8mm) .........................................................................................................19
List of Tables
Table 1: Pin Description ................................................................................................................................................6
Table 2: CH7317A supported Pixel Rates, Clock Rates, Data Transfer Rates and Fill Patterns...................................8
Table 3: Video DAC Configurations for CH7317A ......................................................................................................9
Table 4: Signal Order in the NAND Tree Testing .......................................................................................................10
Table 5: Signals not be tested in NAND Test besides power pins...............................................................................11
Table 6: Revisions .......................................................................................................................................................20
201-0000-087
Rev. 1.2,
12/2/2008
3
CHRONTEL
1.0 Pin-Out
1.1
1.1.1
CH7317A
Package Diagram
The 64-Pin LQFP Package Diagram
SDVO_CLK+
SDVO_CLK-
SDVO_G+
SDVO_R+
SDVO_B+
SDVO_G-
SDVO_R-
SDVO_B-
AGND
AGND
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
NC
SD_DDC
SC_DDC
SD_PROM
SC_PROM
DVDD
RESET*
AS
DGND
DGND
SPD
SPC
DVDD
BSCAN
NC
VDAC2
AGND
AVDD
AVDD
AVDD
RPLL
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NC
VDAC1
GDAC2
NC
DACA[2]
Chrontel
CH7317
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
NC
DACA[0]
NC
GDAC0
ISET
NC
NC
NC
DGND
NC
NC
DVDD
DVDD
XO
XI/FIN
DGND
DGND
BCO/VSYNC
DVDD
C/HSYNC
V3V
NC
DACA[1]
NC
Figure 2: 64-Pin LQFP Package
4
GDAC1
VDAC0
NC
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
201-0000-087
Rev. 1.2,
12/2/2008
CHRONTEL
1.1.2
The 64-Pin QFN Package Diagram
CH7317A
SDVO_CLK+
SDVO_CLK-
SDVO_G+
SDVO_R+
SDVO_B+
SDVO_G-
SDVO_R-
SDVO_B-
AGND
AGND
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AGND
AVDD
AVDD
AVDD
RPLL
NC
NC
SD_DDC
SC_DDC
SD_PROM
SC_PROM
DVDD
RESET*
AS
DGND
DGND
SPD
SPC
DVDD
BSCAN
NC
VDAC2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
NC
NC
NC
DGND
NC
NC
DVDD
DVDD
XO
XI/FIN
DGND
DGND
BCO/VSYNC
DVDD
C/HSYNC
V3V
Chrontel
CH7317
GDAC2
GDAC1
GDAC0
VDAC1
VDAC0
DACA[2]
DACA[1]
DACA[0]
Figure 3: 64-Pin QFN Package
201-0000-087
Rev. 1.2,
12/2/2008
ISET
NC
NC
NC
NC
NC
NC
NC
5
传感器
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