ESMT
SDRAM
M12L32321A
512K x 32Bit x 2Banks
Synchronous DRAM
FEATURES
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Dual banks operation
MRS cycle with address key programs
-
CAS Latency (2 & 3 )
-
Burst Length (1, 2, 4, 8 & full page)
-
Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the
system clock
Burst Read Single-bit Write operation
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle)
GENERAL DESCRIPTION
The M12L32321A is 33,554,432 bits synchronous high data
rate Dynamic RAM organized as 2 x 524,288 words by 32
bits, fabricated with high performance CMOS technology.
Synchronous design allows precise cycle control with the use
of system clock I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst
length and programmable latencies allow the same device to
be useful for a variety of high bandwidth, high performance
memory system applications.
ORDERING INFORMATION
Part NO.
M12L32321A-5BG
M12L32321A-5.5BG
M12L32321A-6BG
M12L32321A-7BG
MAX Freq.
200MHz
183MHz
166MHz
143MHz
PACKAGE COMMENTS
90FBGA
90FBGA
90FBGA
90FBGA
Pb-free
Pb-free
Pb-free
Pb-free
PIN CONFIGURATION (TOP VIEW)
90 Ball FBGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2
3
4
5
6
7
8
9
DQ26 DQ24 VSS
DQ28 VDDQ VSSQ
VSSQ DQ27 DQ25
VSSQ DQ29 DQ30
VDDQ DQ31
VSS DQM3
A4
A7
CLK
DQM1
A5
A8
CKE
NC
NC
A3
A6
NC
A9
NC
VSS
VDD DQ23 DQ21
VDDQ VSSQ DQ19
DQ22 DQ20 VDDQ
DQ17 DQ18 VDDQ
NC
A2
A10
NC
BA
CAS
VDD
DQ6
DQ1
DQ16 VSSQ
DQM2 VDD
A0
NC
CS
WE
A1
NC
RAS
DQM0
VDDQ DQ8
DQ7 VSSQ
DQ5 VDDQ
DQ3 VDDQ
VSSQ DQ10 DQ9
VSSQ DQ12 DQ14
DQ11 VDDQ VSSQ
DQ13 DQ15 VSS
VDDQ VSSQ DQ4
VDD
DQ0
DQ2
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Aug. 2008
Revision
:
1.0
1/28
ESMT
FUNCTIONAL BLOCK DIAGRAM
CLK
CKE
Clock
Generator
Bank B
Row Decoder
M12L32321A
Address
Mode
Register
Row
Address
Buffer
&
Refresh
Counter
Bank A
Sense Amplifier
Command Decoder
Control Logic
CS
RAS
CAS
WE
Data Control Circuit
Input & Output
Buffer
Latch Circuit
Column
Address
Buffer
&
Refresh
Counter
DQM0~3
Column Decoder
DQ
PIN FUNCTION DESCRIPTION
Pin
CLK
CS
CKE
A0 ~ A10
BA
RAS
CAS
WE
Name
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM.
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row / column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10, column address : CA0 ~ CA7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with
CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS ,
WE
active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
Column Address Strobe
Write Enable
Data Input / Output Mask
DQM0~3
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Aug. 2008
Revision
:
1.0
2/28
ESMT
DQ0 ~ 31
VDD/VSS
VDDQ/VSSQ
N.C/RFU
Data Input / Output
Power Supply/Ground
Data Output Power/Ground
No Connection/
Reserved for Future Use
M12L32321A
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved
noise immunity.
This pin is recommended to be left No Connection on the device.
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to V
SS
Voltage on V
DD
supply relative to V
SS
Storage temperature
Power dissipation
Short circuit current
Symbol
V
IN
,V
OUT
V
DD
,V
DDQ
T
STG
P
D
I
OS
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ + 150
0.7
50
Unit
V
V
°
C
W
MA
Note:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
=0 to 70
°C
)
Parameter
Supply voltage
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Output leakage current
Symbol
V
DD
,V
DDQ
V
IH
V
IL
V
OH
V
OL
I
IL
I
OL
Min
3.0
2.0
-0.3
2.4
-
-5
-5
Typ
3.3
3.0
0
-
-
-
-
Max
3.6
V
DD
+0.3
0.8
-
0.4
5
5
Unit
V
V
V
V
V
uA
uA
Note
1
2
I
OH
=-2mA
I
OL
= 2mA
3
4
Note :
1.V
IH
(max) = 4.6V AC for pulse width
≤
10ns acceptable.
2.V
IL
(min) = -1.5V AC for pulse width
≤
10ns acceptable.
3.Any input 0V
≤
V
IN
≤
V
DD
+ 0.3V, all other pins are not under test = 0V.
4.Dout is disabled, 0V
≤
V
OUT
≤
VDD.
CAPACITANCE
(V
DD
= 3.3V, T
A
= 25
°C
, f = 1MHz)
Pin
CLOCK
RAS , CAS ,
WE
, CS , CKE, DQM
ADDRESS
DQ0 ~DQ31
Symbol
C
CLK
C
IN
C
ADD
C
OUT
Min
2.5
2.5
2.5
4.0
Max
4.0
5.0
5.0
6.5
Unit
pF
pF
pF
pF
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Aug. 2008
Revision
:
1.0
3/28
ESMT
DC CHARACTERISTICS
M12L32321A
(Recommended operating condition unless otherwise noted, T
A
= 0 to 70
°C
V
IH
(min)/V
IL
(max)=2.0V/0.8V)
Parameter
Operating Current
(One Bank Active)
Precharge Standby
Current in power-down
mode
Precharge Standby
Current in non
power-down mode
Symbol
Test Condition
CAS
Latency
Version
-5
160
-5.5
160
2
2
25
-6
140
-7
120
Unit Note
mA
mA
mA
mA
1
-
-
-
-
-
-
-
1
1
2
-
I
CC1
I
CC2P
I
CC2PS
I
CC2N
Burst Length = 1
t
RC
≥
t
RC
(min), t
CC
≥
t
CC
(min), I
OL
= 0mA
CKE
≤
V
IL
(max), t
CC
=15ns
CKE
≤
V
IL
(max), CLK
≤
V
IL
(max), t
CC
=
∞
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
=15ns
Input signals are changed one time during 30ns
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
CKE
≤
V
IL
(max), t
CC
=15ns
CKE
≤
V
IL
(max), CLK
≤
V
IL
(max), t
CC
=
∞
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
=15ns
Input signals are changed one time during 30ns
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
I
OL
= 0Ma, Page Burst
All Band Activated, t
CCD
= t
CCD
(min)
t
RC
≥
t
RC
(min)
CKE
≤
0.2V
3
2
I
CC2NS
Active Standby Current
in power-down mode
Active Standby Current
in non power-down
mode
(One Bank Active)
Operating Current
(Burst Mode)
Refresh Current
Self Refresh Current
I
CC3P
I
CC3PS
I
CC3N
I
CC3NS
I
CC4
15
10
10
25
15
160
-
160
160
160
160
1
140
140
140
120
120
120
mA
mA
mA
mA
mA
mA
mA
mA
I
CC5
I
CC6
Note:
1.Measured with outputs open. Addresses are changed only one time during t
CC
(min).
2.Refresh period is 64ms. Addresses are changed only one time during t
CC
(min).
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Aug. 2008
Revision
:
1.0
4/28
ESMT
AC OPERATING TEST CONDITIONS
(V
DD
=3.3V
±
0.3V,T
A
= 0 to 70 °C )
Parameter
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
3.3V
M12L32321A
Value
2.4 / 0.4
1.4
tr / tf = 1 / 1
1.4
See Fig.2
Unit
V
V
ns
V
Vtt =1.4V
1200
Ω
Output
VOH(DC) = 2.4V, IOH = -2mA
VOL(DC) = 0.4V, IOL = 2mA
Output
Z0=50
50
Ω
Ω
870
Ω
30 pF
30 pF
(Fig.1) DC Output Load circuit
(Fig.2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to new col. Address delay
Last data in to row precharge
Last data in to burst stop
Col. Address to col. Address delay
Number of valid output data
Symbol
-5
t
RRD
(min)
t
RCD
(min)
t
RP
(min)
t
RAS
(min)
t
RAS
(max)
t
RC
(min)
t
CDL
(min)
t
RDL
(min)
t
BDL
(min)
t
CCD
(min)
CAS latency=3
CAS latency=2
-
1
55
60
1
2
1
1
2
1
1
10
15
15
32
Version
-5.5
11
16.5
16.5
33
100
60
63
-6
12
18
18
36
-7
14
20
20
42
ns
ns
ns
ns
us
ns
CLK
CLK
CLK
CLK
ea
1
1
1
1
-
1
2
2
2
3
4
Unit
Note
Note:
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
2.
Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks.
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Aug. 2008
Revision
:
1.0
5/28
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