ESMT
Revision History
Revision 0.1 (Dec. 12 2004)
- Original
Revision 1.0 (Jun. 13 2006)
- Add Pb free
Revision 1.1 (Dec. 29 2006)
- Add -5TIG and -5BIG spec
Revision 1.2 (Dec. 13 2007)
- Add BGA type to ordering information
-Modify BGA ball packing dimensions
- Modify Icc2N test condition (/CS <= VIH VIH
- Modify tSHZ timing
-Modify DQ pin capacitance spec
M12L64164A
Operation Temperature Condition -40°C~85°C
/CS >= VIH )
Elite Semiconductor Memory Technology Inc.
Publication Date:
Dec.
2007
Revision: 1.2
1/45
ESMT
SDRAM
M12L64164A
Operation Temperature Condition -40°C~85°C
1M x 16 Bit x 4 Banks
Synchronous DRAM
FEATURES
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
- CAS Latency (2 & 3)
- Burst Length (1, 2, 4, 8 & full page)
- Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the
system clock
DQM for masking
Auto & self refresh
15.6
μ
s refresh interval
ORDERING INFORMATION
PRODUCT NO.
M12L64164A-5TIG
M12L64164A-6TIG
M12L64164A-7TIG
M12L64164A-5BIG
M12L64164A-6BIG
M12L64164A-7BIG
MAX FREQ. PACKAGE Comments
200MHz
166MHz
143MHz
200MHz
166MHz
143MHz
54 TSOP II
54 TSOP II
54 TSOP II
54 VBGA
54 VBGA
54 VBGA
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
GENERAL DESCRIPTION
The M12L64164A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by
16 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on
every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high performance memory system applications.
PIN ASSIGNMENT
Top View
V
DD
DQ 0
V
D D Q
DQ 1
DQ 2
V
S SQ
DQ 3
DQ 4
V
D D Q
DQ 5
DQ 6
V
S SQ
DQ 7
V
DD
LDQ M
WE
C AS
R AS
CS
A
13
A
12
A
10
/AP
A
0
A
1
A
2
A
3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ15
V
S SQ
DQ14
DQ13
V
D D Q
DQ12
DQ11
V
S SQ
DQ10
DQ 9
V
D D Q
DQ 8
V
SS
NC
UDQM
CLK
C KE
NC
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
1
A
VSS
2
DQ15
54 Ball FVBGA (8mmx8mm)
3
VSSQ
4
5
6
7
VDDQ
8
DQ0
9
VDD
B
DQ14
DQ13
VDDQ
VSSQ
DQ2
DQ1
C
DQ12
DQ11
VSSQ
VDDQ
DQ4
DQ3
D
DQ10
DQ9
VDDQ
VSSQ
DQ6
DQ5
E
DQ8
NC
VSS
VDD
LDQM
DQ7
F
UDQM
CLK
CKE
CAS
RAS
WE
G
NC
A11
A9
A13
A12
CS
H
A8
A7
A6
A0
A1
A10
J
VSS
A5
A4
A3
A2
VDD
Elite Semiconductor Memory Technology Inc.
Publication Date:
Dec.
2007
Revision: 1.2
2/45
ESMT
FUNCTIONAL BLOCK DIAGRAM
CLK
CKE
Address
Mode
Register
Clock
Generator
M12L64164A
Operation Temperature Condition -40°C~85°C
Bank D
Bank C
Bank B
Row
Address
Buffer
&
Refresh
Counter
Row Decoder
Bank A
Sense Amplifier
Command Decoder
Control Logic
CS
RAS
CAS
WE
Data Control Circuit
Input & Output
Buffer
Latch Circuit
Column
Address
Buffer
&
Refresh
Counter
L(U)DQM
Column Decoder
DQ
PIN FUNCTION DESCRIPTION
PIN
CLK
CS
CKE
A0 ~ A11
A12 , A13
NAME
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
INPUT FUNCTION
Active on the positive going edge to sample all inputs
Disables or enables device operation by masking or enabling all
inputs except CLK , CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior new command.
Disable input buffers for power down in standby.
Row / column address are multiplexed on the same pins.
Row address : RA0~RA11, column address : CA0~CA7
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
Latches row addresses on the positive going edge of the CLK with
RAS
Row Address Strobe
RAS low.
Enables row access & precharge.
Latches column address on the positive going edge of the CLK with
CAS
Column Address Strobe
CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS ,
WE
active.
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when L(U)DQM active.
Data inputs / outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
This pin is recommended to be left No Connection on the device.
WE
Write Enable
Data Input / Output Mask
Data Input / Output
Power Supply / Ground
Data Output Power / Ground
No Connection
L(U)DQM
DQ0 ~ DQ15
VDD / VSS
VDDQ / VSSQ
NC
Elite Semiconductor Memory Technology Inc.
Publication Date:
Dec.
2007
Revision: 1.2
3/45
ESMT
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Voltage on any pin relative to V
SS
Voltage on V
DD
supply relative to V
SS
Storage temperature
Power dissipation
Short circuit current
Note:
SYMBOL
V
IN
, V
OUT
V
DD
, V
DDQ
T
STG
P
D
I
OS
M12L64164A
Operation Temperature Condition -40°C~85°C
VALUE
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
1
50
UNIT
V
V
°
C
W
mA
Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITION
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -40 to 85
°
C )
PARAMETER
Supply voltage
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Output leakage current
Note:
SYMBOL
V
DD
, V
DDQ
V
IH
V
IL
V
OH
V
OL
I
IL
I
OL
MIN
3.0
2.0
-0.3
2.4
-
-5
-5
0
-
-
-
-
TYP
3.3
MAX
3.6
V
DD
+0.3
0.8
-
0.4
5
5
UNIT
V
V
V
V
V
1
2
I
OH
= -2mA
I
OL
= 2mA
3
4
NOTE
μ
A
μ
A
1. V
IH(max)
= 4.6V AC for pulse width
≤
10ns acceptable.
2. V
IL(min)
= -1.5V AC for pulse width
≤
10ns acceptable.
3. Any input 0V
≤
V
IN
≤
V
DD
+ 0.3V, all other pins are not under test = 0V.
4. D
out
is disabled , 0V
≤
V
OUT
≤
V
DD
.
CAPACITANCE
(VDD = 3.3V, TA = 25
°
C , f = 1MHZ)
PARAMETER
Input capacitance (A0 ~ A11, A13 ~ A12)
Input capacitance
(CLK, CKE, CS , RAS , CAS ,
WE
&
L(U)DQM)
Data input/output capacitance (DQ0 ~ DQ15)
C
IN2
C
OUT
2
2
4
6
pF
pF
SYMBOL
C
IN1
MIN
2
MAX
4
UNIT
pF
Elite Semiconductor Memory Technology Inc.
Publication Date:
Dec.
2007
Revision: 1.2
4/45
ESMT
DC CHARACTERISTICS
M12L64164A
Operation Temperature Condition -40°C~85°C
Recommended operating condition unless otherwise noted，TA = -40 to 85
°
C
PARAMETER
Operating Current
(One Bank Active)
SYMBOL
TEST CONDITION
Burst Length = 1, t
RC
≥
t
RC(min)
, I
OL
= 0 mA,
tcc = tcc(min)
CKE
≤
V
IL(max)
, tcc = tcc(min)
CKE & CLK
≤
V
IL(max)
, tcc =
∞
CKE
≥
V
IH(min)
, CS
≥
V
IH(min)
, tcc = tcc(min)
Input signals are changed one time during 2CLK
CKE
≥
V
IH(min)
, CLK
≤
V
IL(max)
, tcc =
∞
input signals are stable
CKE
≤
V
IL(max)
, tcc = tcc(min)
CKE & CLK
≤
V
IL(max)
, tcc =
∞
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
=15ns
Input signals are changed one time during 2clks
All other pins
≥
V
DD
-0.2V or
≤
0.2V
I
CC3NS
Operating Current
(Burst Mode)
Refresh Current
Self Refresh Current
Note :
I
CC4
I
CC5
I
CC6
CKE
≥
V
IH(min)
, CLK
≤
V
IL(max)
, tcc =
∞
input signals are stable
I
OL
= 0 mA, Page Burst, All Bank active
Burst Length = 4, CAS Latency = 3
t
RC
≥
t
RC(min)
, t
CC
= tcc(min)
CKE
≤
0.2V
180
180
25
150
150
1
140
140
mA
mA
mA
mA
1,2
VERSION
-5
100
-6
85
2
1
20
mA
10
10
10
30
mA
-7
85
UNIT
NOTE
I
CC1
mA
mA
1,2
I
CC2P
Precharge Standby Current
in power-down mode
I
CC2PS
Precharge Standby Current
in non power-down mode
I
CC2N
I
CC2NS
Active Standby Current
in power-down mode
Active Standby Current
in non power-down mode
(One Bank Active)
I
CC3P
I
CC3PS
I
CC3N
mA
1. Measured with outputs open.
2. Input signals are changed one time during 2 CLKS.
Elite Semiconductor Memory Technology Inc.
Publication Date:
Dec.
2007
Revision: 1.2
5/45
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