ESMT
Revision History
Revision1.0 (19 Oct. 2007)
-
Original
M13S2561616A
Operation Temperature Condition -40~85°C
Revision1.1 (06 Dec. 2007)
-
Add BGA package
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2007
Revision : 1.1
1/49
ESMT
DDR SDRAM
Features
JEDEC Standard
Internal pipelined double-data-rate architecture, two data access per clock cycle
Bi-directional data strobe (DQS)
On-chip DLL
Differential clock inputs (CLK and CLK )
DLL aligns DQ and DQS transition with CLK transition
Quad bank operation
CAS Latency : 2; 2.5; 3
Burst Type : Sequential and Interleave
Burst Length : 2, 4, 8
All inputs except data & DM are sampled at the rising edge of the system clock(CLK)
Data I/O transitions on both edges of data strobe (DQS)
DQS is edge-aligned with data for reads; center-aligned with data for WRITE
Data mask (DM) for write masking only
V
DD
= 2.3V ~ 2.7V, V
DDQ
= 2.3V ~ 2.7V
Auto & Self refresh
7.8us refresh interval
SSTL-2 I/O interface
66pin TSOPII and 60 ball BGA package
M13S2561616A
Operation Temperature Condition -40~85°C
4M x 16 Bit x 4 Banks
Double Data Rate SDRAM
Ordering information :
PRODUCT NO.
M13S2561616A -5TIG
M13S2561616A -6TIG
M13S2561616A -5BIG
M13S2561616A -6BIG
MAX FREQ
200MHz
166MHz
200MHz
166MHz
2.5V
BGA
VDD
2.5V
PACKAGE
TSOPII
Pb-free
COMMENTS
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2007
Revision : 1.1
2/49
ESMT
Functional Block Diagram
CLK
CLK
CKE
Address
Mode Register &
Extended Mode
Register
M13S2561616A
Operation Temperature Condition -40~85°C
Clock
Generator
Bank D
Bank C
Bank B
Row Decoder
Row
Address
Buffer
&
Refresh
Counter
Bank A
Sense Amplifier
Command Decoder
Control Logic
CS
RAS
CAS
WE
Data Control Circuit
Input & Output
Buffer
Latch Circuit
Column
Address
Buffer
&
Refresh
Counter
DM
Column Decoder
DQ
CLK, CLK
DLL
DQS
DQS
Pin Arrangement
x16
V
DD
DQ
0
V
DD
Q
DQ
1
DQ
2
V
SSQ
DQ
3
DQ
4
V
DD
Q
DQ
5
DQ
6
V
SSQ
DQ
7
NC
V
DD
Q
LDQ
S
NC
V
DD
NC
LDM
WE
CAS
RAS
CS
NC
BA
0
BA
1
A
10
/AP
A
0
A
1
A
2
A
3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
x
16
V
SS
DQ
15
V
SSQ
DQ
14
DQ
13
V
D
DQ
DQ
12
DQ
11
V
SSQ
DQ
10
DQ
9
V
D
DQ
DQ
8
NC
V
SSQ
UDQS
NC
V
R
EF
V
SS
UDM
CL
K
CL
K
CKE
NC
A1
2
A
1
1
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
66 PIN TSOP(II)
(400mil x 875mil)
(0.65 mm PIN PITCH)
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2007
Revision : 1.1
3/49
ESMT
60 Ball BGA
1
A
B
C
D
E
F
G
H
J
K
L
M
V
SSQ
DQ14
M13S2561616A
Operation Temperature Condition -40~85°C
2
DQ15
V
DDQ
3
V
SS
DQ13
7
V
DD
DQ2
8
DQ0
V
SSQ
9
V
DDQ
DQ1
DQ3
DQ12
DQ10
DQ8
V
REF
V
SSQ
V
DDQ
V
SSQ
V
SS
CLK
DQ11
DQ9
UDQS
DQ4
DQ6
LDQS
V
DDQ
V
SSQ
V
DDQ
V
DD
CAS
CS
BA0
A10/AP
DQ5
DQ7
UDM
CLK
LDM
WE
NC
A12
A11
A8
A6
A4
CKE
A9
A7
A5
RAS
BA1
A0
A2
A1
V
SS
V
DD
A3
Pin Description
Pin Name
Function
Address inputs
- Row address A0~A12
- Column address A0~A8
A10/AP : AUTO Precharge
BA0, BA1 : Bank selects (4 Banks)
Data-in/Data-out
Row address strobe
Column address strobe
Write enable
Ground
Power
Bi-directional Data Strobe. LDQS
corresponds to the data on DQ0~DQ7;
UDQS correspond to the data on
DQ8~DQ15.
Pin Name
Function
DM is an input mask signal for write
data. LDM corresponds to the data
on DQ0~DQ7; UDM correspond to
the data on DQ8~DQ15.
Clock input
Clock enable
Chip select
Supply Voltage for GDQ
Ground for DQ
Reference Voltage for SSTL-2
A0~A12,
BA0,BA1
LDM, UDM
DQ0~DQ15
RAS
CAS
WE
CLK, CLK
CKE
CS
V
DDQ
V
SSQ
V
REF
V
SS
V
DD
LDQS, UDQS
NC
No connection
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2007
Revision : 1.1
4/49
ESMT
Absolute Maximum Rating
Parameter
Voltage on any pin relative to V
SS
Voltage on V
DD
supply relative to V
SS
Voltage on V
DDQ
supply relative to V
SS
Storage temperature
Power dissipation
Short circuit current
Note :
Symbol
V
IN
, V
OUT
V
DD
, V
DDQ
V
DDQ
T
STG
P
D
I
OS
Value
-0.5 ~ 3.6
-1.0 ~ 3.6
-0.5 ~ 3.6
-55 ~ +150
1500
50
M13S2561616A
Operation Temperature Condition -40~85°C
Unit
V
V
V
°C
mW
mA
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operation Condition & Specifications
DC Operation Condition
Recommended operating conditions (Voltage reference to V
SS
= 0V, T
A
= -40 to 85 °C )
Parameter
Supply voltage
I/O Supply voltage
I/O Reference voltage
I/O Termination voltage (system)
Input logic high voltage
Input logic low voltage
Input Voltage Level, CLK and CLK inputs
Input Differential Voltage, CLK and CLK inputs
Input leakage current
Output leakage current
Output High Current (Normal strength driver)
(V
OUT
=V
DDQ
-0.373V, min V
REF
, min V
TT
)
Output Low Current (Normal strength driver)
(V
OUT
= 0.373V)
Symbol
V
DD
V
DDQ
V
REF
V
TT
V
IH
(DC)
V
IL
(DC)
V
IN
(DC)
V
ID
(DC)
I
I
I
OZ
I
OH
I
OL
Min
-5/6
2.3
2.3
0.49*V
DDQ
V
REF
- 0.04
V
REF
+ 0.15
-0.3
-0.3
0.36
-5
-5
-16.8
+16.8
Max
-5/6
2.7
2.7
0.51*V
DDQ
V
REF
+ 0.04
V
DDQ
+ 0.3
V
REF
- 0.15
V
DDQ
+ 0.3
V
DDQ
+ 0.6
5
5
Unit
V
V
V
V
V
V
V
V
1
2
Note
μ
A
μ
A
mA
mA
3
Notes 1. V
REF
is expected to be equal to 0.5* V
DDQ
of the transmitting device, and to track variations in the DC level of the same.
Peak-to-peak noise on V
REF
may not exceed 2% of the DC value.
2. V
TT
is not applied directly to the device. V
TT
is system supply for signal termination resistors, is expected to be set equal
to V
REF
, and must track variations in the DC level of V
REF
.
3. V
ID
is the magnitude of the difference between the input level on CLK and the input level on CLK .
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2007
Revision : 1.1
5/49
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