ESMT
PSRAM
Features
‧Advanced
low-power architecture
• High speed: 55 ns, 70 ns
• Wide voltage range: 2.7V to 3.6V
• Typical active current: 1 mA @ f = 1 MHz
• Low standby power
• Automatic power-down when deselected
M24L216128DA
2-Mbit (128K x 16)
Pseudo Static RAM
Functional Description
The M24L216128DA is a high-performance CMOS pseudo
static RAM (PSRAM) organized as 128K words by 16 bits that
supports an asynchronous memory interface. This device
features advanced circuit design to provide ultra-low active
current. This is ideal for portable applications such as cellular
telephones. The device can be put into standby mode,
reducing power consumption dramatically when deselected
( CE1 HIGH, CE2 LOW or both
BHE
and
BLE
are HIGH).
The input/output pins(I/O
0
through I/O
15
) are placed in a
high-impedance state when the chip is deselected ( CE1
HIGH, CE2 LOW) or OE is deasserted HIGH), or during a
write operation (Chip Enabled and Write Enable
WE
LOW).
Reading from the device is accomplished by asserting the
Chip Enables ( CE1 LOW and CE2 HIGH) and Output Enable
(OE) LOW while forcing the Write Enable (
WE
) HIGH. If Byte
Low Enable (
BLE
) is LOW, then data from the memory
location specified by the address pins will appear on I/O
0
to
I/O
7
. If Byte High Enable (
BHE
) is LOW, then data from
memory will appear on I/O
8
to I/O
15
. Seethe Truth Table for a
complete description of read and write modes.
Logic Block Diagram
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jul. 2008
Revision
:
1.2
1/14
ESMT
Pin Configuration[2, 3, 4]
48-ball VFBGA
Top View
M24L216128DA
44-pin TSOPII
Top View
A4
A3
A2
A1
A0
CE1
I/O0
I/O1
I/O2
I/O3
V
CC
V
SS
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BL E
I/O 1 5
I/O 1 4
I/O 1 3
I/O 1 2
V
SS
V
CC
I/ O1 1
I/ O1 0
I/ O9
I/ O8
CE2
A8
A9
A1 0
A11
NC
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jul. 2008
Revision
:
1.2
2/14
ESMT
Product Portfolio Product
Product
Min.
M24L216128DA
2.7
V
CC
Range (V)
Speed(ns)
Max
3.6
55
70
Operating I
CC
(mA)
f = 1MHz
Typ.[5]
1
Max.
5
f = f
MAX
Typ.[5]
14
8
M24L216128DA
Power Dissipation
Standby I
SB2
(µA)
Typ. [5]
9
Max.
40
Typ.
3.0
Max.
22
15
Note:
2. Ball D3, H1, G2, H6 are the address expansion pins for the 4-Mb, 8-Mb, 16-Mb, and 32-Mb densities respectively.
3. NC “no connect”—not connected internally to the die.
4. DNU (Do Not Use) pins have to be left floating or tied to V
SS
to ensure proper application.
5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC
(typ)
and T
A
= 25 °C .
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jul. 2008
Revision
:
1.2
3/14
ESMT
Maximum Ratings
(Above which the useful life may be impaired. For user
guide-lines, not tested.)
Storage Temperature ...................................–65°C to +150°C
Ambient Temperature with
Power Applied ..............................................–55°C to +125°C
Supply Voltage to Ground Potential . .................−0.4V to 4.6V
DC Voltage Applied to Outputs
in High-Z State[6, 7, 8] .......................................−0.4V to 3.7V
DC Input Voltage[6, 7, 8] ....................................−0.4V to 3.7V
Output Current into Outputs (LOW) ...............................20 mA
M24L216128DA
Static Discharge Voltage ........................................ >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current ....................................................> 200 mA
Operating Range
Range
Extended
Industrial
Ambient
Temperature (T
A
)
−25°C
to +85°C
−40°C
to +85°C
V
CC
2.7V to 3.6V
2.7V to 3.6V
DC Electrical Characteristics (Over the Operating Range)
-55
Parameter
V
CC
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Supply Voltage
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Voltage
Input LOW Voltage
Input Leakage
Current
Output Leakage
Current
V
CC
Operating
Supply Current
Automatic CE1
Power-Down
Current
—CMOS Inputs
Automatic CE1
Power-Down
Current
—CMOS Inputs
Test Conditions
Min.
I
OH
=
−0.1
mA
I
OL
= 0.1 mA
0.8*
V
CC
-0.4
-1
-1
14
1
2.7
V
CC
-
0.4
Typ
.[5]
3.0
Max.
3.6
Min.
2.7
V
CC
-
0.4
0.8*
V
CC
-0.4
-1
-1
8
1
-70
Typ.
[5]
3.0
Unit
Max.
3.6
V
V
0.4
V
CC
+0
.4V
0.4
+1
+1
15
5
mA
V
V
V
µA
µA
0.4
V
CC
+
0.4V
0.4
+1
+1
22
5
f=0
GND
≤
V
IN
≤
V
CC
GND
≤
V
OUT
≤
V
CC
, Output Disabled
f = f
MAX
= 1/t
RC
f = 1 MHz
V
CC
= 3.6V
I
OUT
= 0mA
CMOS levels
I
SB1
CE1
≥
V
CC
−
0.2V, CE2
≤
0.2V, V
IN
≥
V
CC
−
0.2V, V
IN
≤
0.2V, f = f
MAX
(Address and Data Only), f = 0 ( OE ,
WE
,
BHE
and
BLE
), V
CC
=3.6V
40
250
40
250
µA
I
SB2
CE1
≥
V
CC
−0.2V,
CE2
≤
0.2V
V
IN
≥
V
CC
−
0.2V or V
IN
≤
0.2V,
f = 0, V
CC
=3.6V
9
40
9
40
µA
Capacitance[9]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz
V
CC
= V
CC(typ)
Max.
8
8
Unit
pF
pF
Thermal Resistance[9]
Parameter
ΘJA
Description
Thermal Resistance(Junction to Ambient)
Test Conditions
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/ JESD51.
BGA
55
17
Unit
°C/W
°C/W
ΘJC
Thermal Resistance (Junction to Case)
Notes:
6.V
IH(MAX)
= V
CC
+ 0.5V for pulse durations less than 20 ns.
7.V
IL(MIN)
= –0.5V for pulse durations less than 20 ns.
8.Overshoot and undershoot specifications are characterized and are not 100% tested.
9.Tested initially and after any design or process changes that may affect these parameters.
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jul. 2008
Revision
:
1.2
4/14
ESMT
AC Test Loads and Waveforms
M24L216128DA
Parameters
R1
R2
R
TH
V
TH
3.0V V
CC
22000
22000
11000
1.50
Unit
Ω
Ω
Ω
V
Switching Characteristics Over the Operating Range[10]
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
DBE
t
LZBE
t
HZBE
t
SK
[14]
Write Cycle[12]
t
WC
t
SCE
t
AW
t
HA
t
SA
Description
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE1 LOW and CE2 HIGH to Data Valid
OE LOW to Data Valid
OE LOW to LOW Z[11, 12]
OE HIGH to High Z[11, 12]
CE1 LOW and CE2 HIGH to Low Z[11, 12]
CE1 HIGH and CE2 LOW to High Z[11, 12]
BLE
/
BHE
LOW to Data Valid
BLE
/
BHE
LOW to Low Z[11, 12]
BLE
/
BHE
HIGH to High Z[11, 12]
Address Skew
-55 [14]
Min.
Max.
55[14]
55
5
55
25
5
25
2
25
55
5
10
0
55
45
45
0
0
-70
Min.
70
70
10
70
35
5
25
5
25
70
5
25
10
70
55
55
0
0
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle Time
CE1 LOW and CE2 HIGH to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
Notes:
10. Test conditions assume signal transition time of 1 V/ns or higher, timing reference levels of V
CC(typ)
/2, input pulse levels of 0V
to V
CC(typ)
, and output loading of the specified I
OL
/I
OH
and 30-pF load capacitance.
11. t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
transitions are measured when the outputs enter a high-impedance state.
12. High-Z and Low-Z parameters are characterized and are not 100% tested.
13. The internal write time of the memory is defined by the overlap of
WE
, CE1 = V
IL
, CE2 = V
IH
,
BHE
and/or
BLE
= V
IL
.
All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data
input set-up and hold timing should be referenced to the edge of the signal that terminates write.
14. To achieve 55-ns performance, the read access should be Chip-enable controlled. In this case t
ACE
is the critical parameter
and t
SK
is satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must
be stable within 10 ns after the start of the read cycle.
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jul. 2008
Revision
:
1.2
5/14
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