AME, Inc.
AME9003
y
inar
lim
Pre
CCFL Backlight Controller
n
General Description
The AME9003 is AME’ s next generation direct drive
CCFL controller. Like its cousins, the AME9001 and
AME9002, the AME9003 controller provides a cost effi-
cient means to drive single or multiple cold cathode fluo-
rescent lamps (CCFL), driving 3 external MOSFETs that,
in turn, drive a wirewound transformer that is coupled to
the CCFL.
The AME9003, like the AME9002 includes extra cir-
cuitry that allows for a special one second start up pe-
riod wherein the voltage across the CCFL is held at a
higher than normal voltage to allow older tubes (or cold
tubes) a period in which they can” warm up” . During
this one second startup period the driving frequency is
adjusted off of resonance so that the tube voltage can be
controlled. As soon as the CCFL
”
strikes” the special
start up period ends and the circuit operates in its normal
mode. However the AME9003 uses an extra capacitor to
accurately set the start up interval. In addition to that the
AME9003 features a soft start AND soft finish on each
dimming cycle edge in order to minimize any audible
vibrations during the dimming function.
The AME9003 also includes features such as, dimming
control polarity selection, undervoltage lockout and fault
detection. It is designed to work with input voltages from
7V up to 24V. When disabled the circuit goes into a zero
current mode.
n
Pin Configuration
24
23
22
21
20
19
18
17
16
15
14
13
AME9003
1
2
3
4
5
6
7
8
9
10
11
12
AME9003
1. VREF
2. CE
3. SSC
4. RDELTA
5. SSC1ST
6. RT2
7. VSS
8. OVPH
9. OVPL
10.FCOMP
11.CSDET
12.BATTFB
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
OUTC
OUTAPB
OUTA
VBATT
BRPOL
VDD
CT1
FB
COMP
BRIGHT
SSV
PNP
Evaluation Board Available !!
n
System Block Diagram
Controller
External
Components
CCFL Array
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Features
l
Small 24 pin QSOP package
l
24 pin PDIP/SOIC also available
l
Drives multiple tubes
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Special 1 second start up mode
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Automatically checks for common fault
conditions
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7.0V < Vbatt < 24V
l
Low component count
l
Low Idd < 3.5mA
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<1uA shutdown mode
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Battery UV lockout
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Brightness polarity select
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Soft-start, soft-finish dimming
AME
9003
LIGHT
+
Resistors
+
Capacitors
N
n
Applications
l
Notebook computers
l
LCD/TFT displays
1
AME, Inc.
AME9003
y
inar
lim
Pre
CCFL Backlight Controller
n
Pin Description
Pin #
1
Pin Name
VREF
Pin Description
Reference. Compensation point for the 3.4V internal voltage reference. Must have
bypass capacitor connected here to VSS.
Chip enable. When low (<0.4V) the chip is put into a low current (~0uA) shutdown
mode.
Blanking interval ramp. During the first cycle this pin sources 1.5uA. The first cycle is
used to define the initial start up period, often on the order of one second. During
subsequent cycles SSC sources 140mA. This is primarily used to provide a "blanking
interval" at the beginning of every dimming cycle to temporarily disable the fault
protection circuitry. The blanking interval is active when V(SSC) < 3.0 volts. (See
application notes.)
A resistor connected from this pin to VDD determines the amount that the voltage at
FCOMP modulates the switching frequency. The frequency is inversely proportional to
the voltage at FCOMP.
A capacitor added between this pin and SSC is used to define the one second initial
start up period. SSC1ST is connected to VSS for the start up period and floats for
subsequent periods.
A resistor from this pin to VSS sets the minimum frequency of the VCO. The voltage at
this pin is 1.5V
Negative supply. Connect to system ground.
Over voltage protection input (HIGH). Indirectly senses the voltage at the secondary of
the transformer through a resistor (or capacitor) divider. During the initial start up
period, if OVPH is > 3.3V, FCOMP is driven towards VSS (increasing the frequency)
and SSV is reset to zero (which decreases the duty cycle). After the initial start up
period is completed the circuit will shut down if OVPH is > 3.3V.
Over voltage protection input (LOW). During the initial start up period if OVPL < 2.5
volts then FCOMP is allowed to ramp up (decreasing the oscillator frequency allowing
the circuit to get closer to resonance). If, during the initial start up period, OVPL > 2.5
volts then FCOMP is held at its original value (not allowed to increase so the
oscillator frequency stays constant). This action is designed to hold the voltage
across the CCFL constant while the CCFL "warms up".
Frequency control point. Initially this pin is at VSS which yields a maximum switching
frequency. Depending on the voltage at OVPL and OVPH the pin FCOMP will normally
ramp upwards lowering the switching frequency towards the circuit's resonant
frequency.
2
CE
3
SSC
4
RDELTA
5
SSC1ST
6
7
RT2
VSS
8
OVPH
9
OVPL
10
FCOMP
2
AME, Inc.
AME9003
y
inar
lim
Pre
CCFL Backlight Controller
n
Pin Description
Pin #
Pin Name
Pin Description
Current sense detect. Connect this pin to the CCFL current sense resistor divider.
During the initial startup period this pin senses that the CCFL has struck when
V(CSDET) > 1.25 volts. If, after the initial start up period, this pin is below 1.25V for 8
consecutive clock cycles after SSC > 3V then the circuit will shutdown.
UVLO feedback pin. If this pin is above 1.5V then the OUTA pin is allowed to switch, if
below 1.25V then OUTA is disabled.
Drives one of the external NFETs, opposite phase of OUTAPB.
Drives one of the external NFETs, opposite phase of OUTC.
Drives the high side PFET.
Battery input. This is the positive supply for the OUTA driver.
Brightness polarity control. When this pin is low the CCFL brightness increases as
the voltage at the BRIGHT pin increases. When this pin is high the CCFL brightness
decreases
as the voltage at the BRIGHT pin increases.
Regulated 5V supply input.
Sets the dimming cycle frequency. Usually about 100Hz.
Negative input of the voltage control loop error amplifier.
Output of the voltage control loop error amplifier.
Brightness control input. A DC voltage on this controls the duty cycle of the dimming
cycle. This pin is compared to a 3V ramp at the CT1 pin. Analog brightness control
may be accomplished by small modifications to the external circuitry.
Soft start ramp for the voltage control loop. (20uA source current.) The voltage at SSV
clamps the voltage at COMP to be no greater than SSV thereby limiting the increase of
the switching duty cycle.
Drives the base of an external PNP transistor used for the 5V LDO.
11
CSDET
12
13
14
15
16
BATTFB
OUTC
OUTAPB
OUTA
VBATT
17
BRPOL
18
19
20
21
VDD
CT1
FB
COMP
22
BRIGHT
23
SSV
24
PNP
3
AME, Inc.
AME9003
y
inar
lim
Pre
CCFL Backlight Controller
n
Ordering Information
AME9003 x x x x x
Special Feature
Number of Pins
Package Type
Operating Temperature Range
Pin Configuration
Pin Configuration
Operating
Temperature Range
Package Type
Number of
Pins
Special Feature
A: 1 .
2 .
3 .
4 .
5 .
6 .
7 .
8 .
9 .
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
VREF
CE
SSC
RDELTA
FAULTB
RT2
VSS
OVPH
OVPL
FCOMP
CSDET
BATTFB
OUTC
OUTAPB
OUTA
VBATT
BRPOL
VDD
CT1
FB
COMP
BRIGHT
SSV
PNP
E: -40
O
C to 85
O
C
J: SOIC (300 mil)
P: Plastic DIP
T: QSOP
H: 24
Z: Lead free
4
AME, Inc.
AME9003
y
inar
lim
Pre
CCFL Backlight Controller
n
Ordering Information (contd.)
Part Number
AME9003AETH
Marking*
AME9003AETH
xxxxxxxx
yyww
AME9003AETH
xxxxxxxx
yyww
AME9003AEPH
xxxxxxxx
yyww
AME9003AEPH
xxxxxxxx
yyww
AME9003AEJH
xxxxxxxx
yyww
AME9003AEJH
xxxxxxxx
yyww
Output Voltage
N/A
Package
QSOP-24
Operating Temp. Range
- 40
o
C to + 85
o
C
AME9003AETHZ
N/A
QSOP-24
- 40
o
C to + 85
o
C
AME9003AEPH
N/A
PDIP-24
- 40
o
C to + 85
o
C
AME9003AEPHZ
N/A
PDIP-24
- 40
o
C to + 85
o
C
AME9003AEJH
N/A
SOIC-24
- 40
o
C to + 85
o
C
AME9003AEJHZ
N/A
SOIC-24
- 40
o
C to + 85
o
C
Note: yyww represents the date code
* A line on top of the first letter represents lead free plating such as AME9003
Please consult AME sales office or authorized Rep./Distributor for the availability of output voltage and package type .
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