SPLC563A
320-Channel Low-Voltage Segment
Driver for Dot-Matrix STN Liquid
Crystal Display
MAY. 16, 2005
Version 1.0
Sunplus Technology reserves the right to change this documentation without prior notice. Information provided by Sunplus Technology is believed to be
accurate and reliable.
However, Sunplus Technology makes no warranty for any errors which may appear in this document.
Contact Sunplus Technology to
obtain the latest version of device specifications before placing your order.
No responsibility is assumed by Sunplus Technology for any infringement of
patent or other rights of third parties which may result from its use. In addition, Sunplus products are not authorized for use as critical components in life
support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury
to the user, without the express written approval of Sunplus.
SPLC563A
Table of Contents
PAGE
1. GENERAL DESCRIPTION .......................................................................................................................................................................... 3
2. FEATURES .................................................................................................................................................................................................. 3
3. BLOCK DIAGRAM ...................................................................................................................................................................................... 3
3.1. B
LOCK
F
UNCTION
D
ESCRIPTIONS
........................................................................................................................................................... 4
3.1.1. Liquid crystal drive circuit .......................................................................................................................................................... 4
3.1.2. Level shifter............................................................................................................................................................................... 4
3.1.3. Latch circuit 2 ............................................................................................................................................................................ 4
3.1.4. Latch circuit 1 ............................................................................................................................................................................ 4
3.1.5. Shift register.............................................................................................................................................................................. 4
3.1.6. Data rearrangement circuit ....................................................................................................................................................... 4
3.1.7. Timing generator circuit............................................................................................................................................................. 4
4. SIGNAL DESCRIPTIONS............................................................................................................................................................................ 5
5. REARRANGING OUTPUT DATA (SHL)...................................................................................................................................................... 7
6. OPERATION TIMING .................................................................................................................................................................................. 8
6.1. 4-B
IT
C
APTURE
M
ODE
(1
LINE
, 640
DOTS
)............................................................................................................................................... 8
6.2. 8-B
IT
C
APTURE
M
ODE
(1
LINE
, 640
DOTS
)............................................................................................................................................... 9
7. ELECTRICAL SPECIFICATIONS ............................................................................................................................................................. 10
7.1. A
BSOLUTE
M
AXIMUM
R
ATINGS
............................................................................................................................................................. 10
7.1.1. Turning on the power ...............................................................................................................................................................11
7.1.2. Turning off the power ...............................................................................................................................................................11
7.2. DC C
HARACTERISTICS
1 .......................................................................................................................................................................11
7.3. DC C
HARACTERISTICS
2 ...................................................................................................................................................................... 12
7.4. AC C
HARACTERISTICS
1 ...................................................................................................................................................................... 13
7.5. AC C
HARACTERISTICS
2 ...................................................................................................................................................................... 14
8. APPLICATION CIRCUIT ........................................................................................................................................................................... 16
9. PACKAGE/PAD LOCATIONS ................................................................................................................................................................... 17
9.1. PAD A
SSIGNMENT AND
L
OCATIONS
....................................................................................................................................................... 17
9.2. O
RDERING
I
NFORMATION
..................................................................................................................................................................... 17
10. DISCLAIMER............................................................................................................................................................................................. 18
11. REVISION HISTORY ................................................................................................................................................................................. 19
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© Sunplus Technology Co., Ltd.
Proprietary & Confidential
2
MAY. 16, 2005
Version: 1.0
SPLC563A
320-CHANNEL LOW-VOLTAGE SEGMENT
DRIVER FOR DOT-MATRIX STN LIQUID CRYSTAL DISPLAY
1. GENERAL DESCRIPTION
The SPLC563A is a 320-channel segment driver for driving a
dot-matrix STN liquid-crystal panel at a low voltage.
The driver
can also correspond to 240-channel output by switching mode. It
operates at a low voltage: a liquid-crystal drive voltage of 5.0V and
a logic drive voltage of 3.0V, and is used together with common
driver SPLC564A.
can be applied to various liquid crystal panels.
2. FEATURES
Display duty: Up to 1/240
Liquid crystal drive voltage: 2.6V to 5.5V
Number of liquid crystal drive circuits: 320 circuits
Operating voltage: 2.5V to 5.5V
Number of data bits: 4 or 8 bits
3. BLOCK DIAGRAM
V0L
VML
V1L
VCC
GND2
GND1
CL1
M
BS
D0-D7
SHL
MODE
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The package, which adopts a flexible TCP,
Shift clock speed: 8.0MHz max @ 5.0V, 6.5MHz max @ 3.0V
Together with the common drivers SPLC564A
Low power consumption
Display-off function
Flexible TCP
Switching output mode: 320 output mode, 240 output mode
Automatic generation of chip-enable signals
Standby function
Y0 - Y319
Liquid crystal drive circuit
*
V0L
VML
V1L
Level shifter
Level
shifter
Timing
generator
circuit
Latch circuit 2
DISPOFF
Latch circuit 1
Latch circuit 1
Data
rearrangement
circuit
CL2
Shift register
EIO1
EIO2
Note:
PINs V0L, VML, and V1L are internally connected to pins V0R, VMR, and V1R, respectively.
© Sunplus Technology Co., Ltd.
Proprietary & Confidential
3
MAY. 16, 2005
Version: 1.0
SPLC563A
3.1. Block Function Descriptions
3.1.1. Liquid crystal drive circuit
Selects and outputs the liquid crystal drive level V0, VM, or V1 by
3.1.5. Shift register
80-bit shift register, which generates data-capture signals for latch
circuits 1 at the fall of CL2.
DISPOFF
and a combination of data for latch circuit 2 and signal
M.
3.1.6. Data rearrangement circuit
Inverts the order of data output crosswise.
3.1.2. Level shifter
Converts logic signals to liquid crystal drive signals.
3.1.7. Timing generator circuit
The timing generator circuit generates data latch pulses for latch
circuit2 and changes pulse the LCD drive outputs to AC.
3.1.3. Latch circuit 2
320-bit latch circuit, which latches the data of latch circuits 1 at the
fall of CL1 and outputs the data to the level shifter.
3.1.4. Latch circuit 1
4/8-bit parallel data latch circuit, which latches display data D0 to
D7 according to signals transmitted from the shift register.
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© Sunplus Technology Co., Ltd.
Proprietary & Confidential
4
MAY. 16, 2005
Version: 1.0
SPLC563A
4. SIGNAL DESCRIPTIONS
Classification
Power
supply
Symbol
VCC
GND1
GND2
V0L
V0R
VML
VMR
V1L
V1R
CL1
CL2
M
PAD No.
347
353
385
342
391
339
394
345
388
V0L
V0R
VML
VMR
V1L
V1R
Input
Liquid crystal drive level power supply
V0
VM
V1
Connected to
VCC
GND
I/O
-
Functions
VCC - GND: Power supply for logic.
Control
signal
DISPOFF
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379
377
Clock 1
Clock 2
M
Input
Latch signal of display data: A liquid crystal drive signal
corresponding to display data is output at the fall of CL1.
fall of CL2.
Input
Capture signal of display data: Display data is captured at the
A.C. signal of liquid crystal drive output
Display data
Liquid crystal drive output
Selected level
381
Input
D0 to D7
361, 369
363, 371
365, 373
367, 375
355
357
DATA0 to
DATA7
Input
Liquid crystal drive output
ON
1 (VCC level)
0 (GND level)
Not-selected level
OFF
SHL
Shift Left
Input
I/O
Control signal for inverting the order of data output (see the
following page)
SHL
EIO1
Enable IO1
EIO1
EIO2
GND
VCC
Enable input
Enable Output
Enable input
Enable output
EIO2
383
Enable IO2
I/O
Enable input: The enable input of the first IC is connected to the
GND and another is connected to the enable output of the
second IC.
Enable output: Connected to the enable input of the second IC
at cascade output.
Grounding
DISPOFF
sets liquid crystal drive output Y0 - Y319
to the VM level.
359
Disp off
Input
BS
351
Bus Select
Input
Switches the number of input bits for the display data.
VCC
8-bit input mode
GND
4-bit input mode (Captures data from D0 - D3. At this time,
connect D4 - D7 to the GND.)
MODE
349
MODE
Input
Switches the number of input bits for the display data.
VCC
GND
320 output mode
240 output mode (Y40 - Y279 are valid output. The other
80 pins output the not-selected-level signals synchronized
every time; release these pins.)
© Sunplus Technology Co., Ltd.
Proprietary & Confidential
5
MAY. 16, 2005
Version: 1.0
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