ESMT
PSRAM
Features
•Advanced low-power architecture
•High speed: 55 ns, 70 ns
•Wide voltage range: 2.7V to 3.3V
•Typical active current: 1 mA @ f = 1 MHz
•Low standby power
•Automatic power-down when deselected
M24L28256DA
2-Mbit (256K x 8)
Pseudo Static RAM
Enable (
WE
) inputs LOW and Chip Enable Two ( CE
2
) input
HIGH. Data on the eight I/O pins (I/O
0
through I/O
7
) is then
written into the location specified on the address pins (A
0
through A
17
).
Reading from the device is accomplished by asserting the
Chip Enable One ( CE
1
) and Output Enable ( OE ) inputs
LOW while forcing Write Enable (
WE
) HIGH. And Chip
Enable Two ( CE
2
) HIGH. Under these conditions, the
contents of the memory location specified by the address pins
will appear on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected ( CE
1
HIGH or CE
2
LOW), the outputs are disabled ( OE HIGH), or
during write operation ( CE
1
LOW, CE
2
HIGH, and
WE
LOW). See the Truth Table for a complete description of read
and write modes.
Functional Description
The M24L28256DA is a high-performance CMOS pseudo
static RAM (PSRAM) organized as 256K words by 8 bits.
Easy memory expansion is provided by an active LOW Chip
Enable( CE
1
) and active HIGH Chip Enable ( CE
2
),and active
LOW Output Enable ( OE ).This device has an automatic
power-down feature that reduces power consumption
dramatically when deselected. Writing to the device is
accomplished by asserting Chip Enable One ( CE
1
) and Write
Logic Block Diagram
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jul. 2007
Revision
:
1.0
1/10
ESMT
Pin Configuration[1]
VFBGA
Top View
M24L28256DA
Product Portfolio
Power Dissipation
V
CC
Range (V)
Product
Min.
M24L28256DA
2.7
Typ.
3.0
Max.
3.3
55
70
Speed(ns)
f = 1MHz
Typ.[2]
1
Max.
5
f = f
MAX
Typ.[2]
14
8
Max.
22
15
Typ. [2]
9
Max.
40
Operating I
CC
(mA)
Standby I
SB2
(µA)
Notes:
1. NC “no connect”—not connected internally to the die.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
and T
A
= 25°C.
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jul. 2007
Revision
:
1.0
2/10
ESMT
Maximum Ratings
(Above which the useful life may be impaired. For user
guide-lines, not tested.)
Storage Temperature ...................................–65°C to +150°C
Ambient Temperature with
Power Applied ..............................................–40°C to +85°C
Supply Voltage to
Ground Potential . ............... ............ ...........−0.4V to 4.6V
DC Voltage Applied to Outputs
in High-Z State[3, 4, 5] .................................−0.4V to 3.7V
DC Input Voltage[3, 4, 5].................... .........−0.4V to 3.7V
Output Current into Outputs (LOW) ...............................20 mA
M24L28256DA
Static Discharge Voltage ........................................ >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current ....................................................> 200 mA
Operating Range
Range
Extended
Ambient
Temperature (T
A
)
−25°C
to +85°C
V
CC
2.7V to 3.3V
Electrical Characteristics
(Over the Operating Range)
-55
Parameter
V
CC
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Supply Voltage
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Voltage
Input LOW
Voltage
Input Leakage
Current
Output Leakage
Current
V
CC
Operating
Supply Current
Automatic CE
1
Power-Down
Current
—CMOS Inputs
Automatic CE
1
Power-Down
Current
—CMOS Inputs
Test Conditions
Min.
I
OH
=
−0.1
mA
I
OL
= 0.1 mA
0.8*
V
CC
-0.4
GND
≤
V
IN
≤
V
CC
GND
≤
V
OUT
Disable
f = f
MAX
= 1/t
RC
f = 1 MHz
-1
-1
14
1
2.7
V
CC
-
0.4
Typ.
[2]
3.0
Max.
3.3
Min.
2.7
V
CC
-
0.4
0.8*
V
CC
-0.4
-1
-1
8
1
-70
Typ.
[2]
Unit
Max.
3.3
V
V
0.4
V
CC
+0.4
0.4
+1
+1
15
5
mA
V
V
V
µA
µA
0.4
V
CC
+
0.4
0.4
+1
+1
22
5
≤
V
CC
, Output
V
CC
= 3.3V
I
OUT
= 0mA
CMOS levels
I
SB1
CE
1
≥
V
CC
−0.2V,
CE
2
≤
0.2V
V
IN
≥
V
CC
−
0.2V, V
IN
≤
0.2V,
f = f
MAX
(Address and Data Only),
f=0
CE
1
≥
V
CC
−0.2V,
CE
2
≤
0.2V
V
IN
≥
V
CC
−
0.2V, V
IN
≤
0.2V,
f = 0, V
CC
= 3.3V
40
250
40
250
µA
I
SB2
9
40
9
40
µA
Capacitance[6]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz
V
CC
= V
CC(typ)
Max.
8
8
Unit
pF
pF
Thermal Resistance[6]
Parameter
Θ
JA
Θ
JC
Description
Thermal Resistance(Junction to Ambient)
Thermal Resistance (Junction to Case)
Test Conditions
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/ JESD51.
BGA
55
17
Unit
°C/W
°C/W
Notes:
3.V
IH(MAX)
= V
CC
+ 0.5V for pulse durations less than 20 ns.
4.V
IL(MIN)
= –0.5V for pulse durations less than 20 ns.
5.Overshoot and undershoot specifications are characterized and are not 100% tested.
6.Tested initially and after design or process changes that may affect these parameters.
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jul. 2007
Revision
:
1.0
3/10
ESMT
AC Test Loads and Waveforms
M24L28256DA
Parameters
R1
R2
R
TH
V
TH
3.0V (V
CC
)
22000
22000
11000
1.50
Unit
Ω
Ω
Ω
V
Switching Characteristics
(Over the Operating Range) [7]
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
SK[
11]
Write Cycle
[10]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Description
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
LOW and CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Z[8, 9]
OE HIGH to High Z[8, 9]
CE
1
LOW and CE
2
HIGH to LOW Z[8, 9]
CE
1
HIGH and CE
2
LOW to HIGH Z[ 8, 9]
Address Skew
Write Cycle Time
CE
1
LOW and CE
2
HIGH to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE
Pulse Width
-55
Min.
55[11]
55
5
55
25
5
25
5
25
0
55
45
45
0
0
40
25
0
25
5
5
70
55
55
0
0
55
25
0
5
5
10
Max.
Min.
70
-70
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
70
70
35
25
25
10
Data Set-Up to Write End
Data Hold from Write End
WE
LOW to High-Z[8, 9]
WE
HIGH to Low-Z[8, 9]
25
ns
ns
Notes:
7. Test conditions assume signal transition time of 1V/ns or higher, timing reference levels of V
CC(typ)
/2, input pulse levels of 0V
to V
CC(typ)
, and output loading of the specified I
OL
/I
OH
and 30-pF load capacitance
8. t
HZOE
, t
HZCE
, and t
HZWE
transitions are measured when the outputs enter a high-impedance state.
9. High-Z and Low-Z parameters are characterized and are not 100% tested.
10. The internal write time of the memory is defined by the overlap of
WE
, CE
1
= V
IL
, and CE
2
=V
IH
. All signals must be
ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold
timing should be referenced to the edge of the signal that terminates write.
11. To achieve 55-ns performance, the read access should be CE controlled. In this case t
ACE
is the critical parameter and t
SK
is satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be
stable within 10 ns after the start of the read cycle.
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jul. 2007
Revision
:
1.0
4/10
ESMT
Switching Waveforms
Read Cycle 1 (Address Transition Controlled)[11,
12, 13]
M24L28256DA
Read Cycle 2
(
OE
Controlled)
[11, 13]
Notes:
12. Device is continuously selected. OE , CE
1
=V
IL
and CE
2
= V
IH
.
13.
WE
is HIGH for Read Cycle.
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jul. 2007
Revision
:
1.0
5/10
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