ESMT
Revision History
Revision 0.1(May. 13 2005)
-Original
Revision 0.2 (Aug. 08 2005)
-Delete Non-Pb-free of ordering information
Revision 1.0 (Dec. 22 2005)
-Delete “Preliminary” from datasheet
-Add 90BGA Packing Dimension
Revision 1.1 (Feb. 14 2006)
-Modify ICC4, ICC5 spec
Revision 1.2 (Mar. 14 2006)
-Modify ICC2N, ICC3N spec
M12L128324A
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2006
Revision: 1.2
1/47
ESMT
SDRAM
M12L128324A
1M x 32 Bit x 4 Banks
Synchronous DRAM
FEATURES
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
- CAS Latency (1, 2 & 3 )
- Burst Length ( 1, 2, 4, 8 & full page )
- Burst Type ( Sequential & Interleave )
All inputs are sampled at the positive going edge of the
system clock
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle)
ORDERING INFORMATION
Product No.
M12L128324A-6TG
M12L128324A-7TG
M12L128324A-6BG
M12L128324A-7BG
MAX FREQ. PACKAGE COMMENTS
166MHz
143MHz
166MHz
143MHz
86L TSOPII
86L TSOPII
90 FBGA
90 FBGA
Pb-free
Pb-free
Pb-free
Pb-free
GENERAL DESCRIPTION
The M12L128324A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 32 bits.
Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system applications.
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2006
Revision: 1.2
2/47
ESMT
PIN ARRANGEMENT
Top View
V
DD
DQ0
V
D
DQ
M12L128324A
DQ1
DQ2
V
SSQ
DQ3
DQ4
V
D DQ
DQ5
DQ6
V
SSQ
DQ7
NC
V
DD
D Q M0
WE
C AS
R AS
CS
A 11
BA0
BA1
A1 0/AP
A0
A1
A2
D Q M2
V
D D
NC
D Q 16
V
S SQ
D Q 17
D Q 18
V
DDQ
D Q 19
D Q 20
V
S SQ
D Q 21
D Q 22
V
D DQ
D Q 23
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
V
S
S
D Q 15
V
S SQ
D Q 14
D Q 13
V
D DQ
D Q 12
D Q 11
V
S SQ
D Q 10
DQ9
V
D DQ
DQ8
NC
V
S
S
DQM 1
NC
NC
C LK
C KE
A9
A8
A7
A6
A5
A4
A3
DQM 3
V
S
S
NC
DQ3 1
V
D DQ
DQ3 0
DQ2 9
V
S SQ
DQ2 8
DQ2 7
V
D DQ
DQ2 6
DQ2 5
V
S SQ
DQ2 4
V
S S
86Pi n T SO P( II)
( 4 0 0 m il x 8 7 5 m i l)
( 0 . 5 m m P in p i t c h )
90 Ball FBGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2
3
4
5
6
7
8
9
DQ26 DQ24 VSS
DQ28 VDDQ VSSQ
VSSQ DQ27 DQ25
VSSQ DQ29 DQ30
VDDQ DQ31
VSS DQM3
A4
A7
CLK
DQM1
A5
A8
CKE
NC
NC
A3
A6
NC
A9
NC
VSS
VDD DQ23 DQ21
VDDQ VSSQ DQ19
DQ22 DQ20 VDDQ
DQ17 DQ18 VDDQ
NC
A2
A10
NC
BA0
CAS
VDD
DQ6
DQ1
DQ16 VSSQ
DQM2 VDD
A0
BA1
CS
WE
A1
A11
RAS
DQM0
VDDQ DQ8
DQ7 VSSQ
DQ5 VDDQ
DQ3 VDDQ
VSSQ DQ10 DQ9
VSSQ DQ12 DQ14
DQ11 VDDQ VSSQ
DQ13 DQ15 VSS
VDDQ VSSQ DQ4
VDD
DQ0
DQ2
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2006
Revision: 1.2
3/47
ESMT
BLOCK DIAGRAM
CLK
CKE
Address
Mode
Register
Clock
Generator
Bank D
Bank C
Bank B
Row
Address
Buffer
&
Refresh
Counter
Row Decoder
M12L128324A
Bank A
Sense Amplifier
Command Decoder
Control Logic
CS
RAS
CAS
WE
Data Control Circuit
Input & Output
Buffer
Latch Circuit
Column
Address
Buffer
&
Refresh
Counter
DQM0~3
Column Decoder
DQ
PIN DESCRIPTION
PIN
CLK
CS
CKE
A0 ~ A11
BA0 , BA1
RAS
NAME
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
INPUT FUNCTION
Active on the positive going edge to sample all inputs
Disables or enables device operation by masking or enabling all
inputs except CLK , CKE and DQM0-3.
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior new command.
Disable input buffers for power down in standby.
Row / column address are multiplexed on the same pins.
Row address : RA0~RA11, column address : CA0~CA7
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
Latches row addresses on the positive going edge of the CLK with
RAS low.
Enables row access & precharge.
Latches column address on the positive going edge of the CLK with
CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS ,
WE
active.
CAS
Column Address Strobe
WE
Write Enable
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2006
Revision: 1.2
4/47
ESMT
PIN
DQM0~3
DQ0 ~ DQ31
V
DD
/ V
SS
V
DDQ
/ V
SSQ
N.C
NAME
Data Input / Output Mask
Data Input / Output
Power Supply / Ground
Data Output Power / Ground
No Connection
M12L128324A
INPUT FUNCTION
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when DQM active.
Data inputs / outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
This pin is recommended to be left No Connection on the device.
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to V
SS
Voltage on V
DD
supply relative to V
SS
Storage temperature
Power dissipation
Short circuit current
Note :
Symbol
V
IN
, V
OUT
V
DD
, V
DDQ
T
STG
P
D
I
OS
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
1
50
Unit
V
V
°
C
W
mA
Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITION
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= 0 to 70 °C )
Parameter
Supply voltage
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Output leakage current
Note:
Symbol
V
DD
, V
DDQ
V
IH
V
IL
V
OH
V
OL
I
IL
I
OL
Min
3.0
2.0
-0.3
2.4
-
-5
-5
Typ
3.3
3.0
0
-
-
-
-
Max
3.6
V
DD
+0.3
0.8
-
0.4
5
5
Unit
V
V
V
V
V
1
2
I
OH
= -2mA
I
OL
= 2mA
3
4
Note
μ
A
μ
A
1. V
IH
(max) = 4.6V AC for pulse width
≤
10ns acceptable.
2. V
IL
(min) = -1.5V AC for pulse width
≤
10ns acceptable.
3. Any input 0V
≤
VIN
≤
V
DD
+ 0.3V, all other pins are not under test = 0V.
4. Dout is disabled , 0V
≤
V
OUT
≤
V
DD
.
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2006
Revision: 1.2
5/47
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