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SGRAM
FEATURES
O
JEDEC standard 3.3V power supply
O
LVTTL compatible with multiplexed address
O
Dual bank / Pulse RAS
O
MRS cycle with address key programs
M32L1632512A
256K x 32 Bit x 2 Banks
Synchronous Graphic RAM
GENERAL DESCRIPTION
The M32L1632512A is 16, 777, 216 bits synchro-
nous high data rate Dynamic RAM organized as 2 x
262, 144 words by 32 bits, fabricated with ESMT’s
high performance CMOS technology. Synchronous
design allows precise cycle control with the use of
system clock. I/O transactions are possible on every
clock cycle. Range of operating frequencies , progra-
mmable burst length, and programmable latencies
allows the same device to be useful for a variety of
high bandwidth, high performance memory system
applications.
Write per bit and 8 columns block write improves
performance in graphic systems.
O
O
O
O
O
O
- CAS Latency ( 2, 3 )
- Burst Length ( 1, 2, 4, 8 & full page )
- Burst Type ( Sequential & Interleave )
All inputs are sampled at the positive going
edge of the system clock
Burst Read Single-bit Write operation
DQM 0-3 for byte masking
Auto & self refresh
32ms refresh period (2K cycle)
100 pin QFP
Graphic Features
O
SMRS cycle
ORDERING INFORMATION
- Load mask register
- Load color register
O
Write Per Bit
O
Block Write (8 Columns)
Part NO.
M32L1632512A-5Q
M32L1632512A-5SQ
M32L1632512A-6Q
M32L1632512A-6SQ
M32L1632512A-7Q
M32L1632512A-7SQ
M32L1632512A-8Q
M32L1632512A-8SQ
Cycle
time
5ns
5ns
6ns
6ns
7ns
7ns
8ns
8ns
Clock
Access
t
RDL
Frequency time@CL=3 (clk)
200MHz
200MHz
166MHz
166MHz
143MHz
143MHz
125MHz
125MHz
4.5ns
4.5ns
5.5ns
5.5ns
6.0ns
6.0ns
6.5ns
6.5ns
1
2
1
2
1
2
1
2
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jun. 2001
Revision
:
1.6
1/54
$ %
FUNCTIONAL BLOCK DIAGRAM
DQMi
BLOCK
WRITE
CONTROL
LOGIC
CLK
CKE
CS
RAS
CAS
WE
DSF
DQMi
SERIAL
COUNTER
COLUMN ADDRESS
BUFFER
TIMING REGISTER
COLUMN
MASK
LATENCY &
BURST LENGTH
M32L1632512A
MASK
REGISTER
WRITE
CONTROL
LOGIC
MASK
MUX
COLOR
REGISTER
INPUT BUFFER
DQMi
DQi
(i=0~31)
PROGRAMING
REGISTER
COLUMN
DECORDER
SENSE
AMPLIFIER
256Kx32
CELL
ARRAY
256Kx32
CELL
ARRAY
ROW DECORDER
BANK SELECTION
ROW ADDRESS
BUFFER
REFRESH
COUNTER
ADDRESS REGISTER
CLOCK
ADDRESS(A
0
~A
10
)
PIN CONFIGURATION (TOP VIEW)
DQM3
VDDQ
DQ15
DQ25
DQ28
DQ27
DQ26
DQ24
DQ14
V
DDQ
V
SSQ
DQM1
DQ11
DQ13
DQ12
V
DDQ
DQ10
V
DDQ
V
SSQ
V
SSQ
DQ 9
DQ 8
CLK
CKE
DSF
V
DD
N. C
V
SS
N. C
A
9
80
79
78
77
76
75
74
71
73
72
70
69
68
67
66
65
64
63
62
61
60
59
58
57
54
53
56
55
DQ29
VSSQ
DQ30
DQ31
VSS
N. C
N. C
N. C
N. C
N. C
N. C
N. C
N. C
N. C
N. C
V
DD
DQ 0
DQ 1
VSSQ
DQ 2
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
10 0
10
11
12
13
14
15
16
17
18
19
20
21
23
24
27
28
22
25
26
29
30
1
2
3
4
5
6
7
8
9
1 0 0
P in
Q F P
T y p e
m m
P itc h
52
51
50
49
48
47
46
45
44
43
F o rw a rd
2 0
0 .6 5
x
1 4
42
41
40
39
38
37
36
35
34
33
32
31
A7
A6
A5
A4
VSS
N. C
N. C
N. C
N. C
N. C
N. C
N. C
N. C
N. C
N. C
VDD
A3
A2
A1
A0
m m p in
DQ 6
DQ 7
V
DDQ
V
SSQ
CS
BA(A
10
)
V
SSQ
DQ3
V
DDQ
DQ4
DQ5
DQ16
DQ17
DQ18
DQ19
V
DDQ
DQ21
V
SSQ
WE
DQM0
DQM2
DQ20
DQ23
V
DDQ
CAS
DQ22
RAS
V
DD
V
SS
Elite Semiconductor Memory Technology Inc.
A
8
Publication Date
:
Jun. 2001
Revision
:
1.6
2/54
OUTPUT BUFFER
$ %
PIN DESCRIPTION
PIN
CLK
CS
CKE
NAME
System Clock
Chip Select
Clock Enable
INPUT FUNCTION
M32L1632512A
Active on the positive going edge to sample all inputs
Disables or enable device operation by masking or enabling all
inputs except CLK, CKE and DQMi
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one clock+
t
ss prior to new
command.
Disable input buffers for power down in standby.
Row / column addresses are multiplexed on the same pins.
Row address : RA0~RA9, column address : CA0~CA7
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
Latches row addresses on the positive going edge of the CLK with
RAS low.
Enables row access & precharge.
Latches column address on the positive going edge of the CLK
With
CAS low.
Enables column access.
Enables write operation and Row precharge.
Makes data output Hi-Z,
t
SHZ
after the clock and masks the output.
Blocks data input when DQM active. (Byte Masking)
Data inputs/outputs are multiplexed on the same pins.
Enables write per bit, block write and special mode register set.
A0 ~ A9
A10(BA)
RAS
Address
Bank Select Address
Row Address Strobe
CAS
Column Address Strobe
WE
DQMi
DQi
DSF
V
DD
/V
SS
V
DDQ
/V
SSQ
Write Enable
Data Input/Output Mask
Data Input/Output
Define Special/ Function
Power Supply/ Ground
Data Output Power/Ground
ABSOLUTE MAXIMUM RATINGS
(Voltage referenced to V
SS
)
Parameter
Voltage on any pin relative to V
SS
Voltage on V
DD
supply relative to V
SS
Storage temperature
Power dissipation
Short circuit current
Symbol
V
IN
, V
OUT
V
DD
, V
DDQ
T
STG
P
D
I
OS
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
1
50
Unit
V
V
i
W
mA
Note :
Permanent device damage may occur if “ABSOLUTE MAXIMUM RATINGS” are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device
reliability.
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jun. 2001
Revision
:
1.6
3/54
$ %
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to V
SS
= 0V)
Parameter
Supply voltage
Input high voltage
Input low voltage
Output high voltage
Output low voltage
Input leakage current
Output leakage current
Output Loading Condition
Symbol
V
DD
, V
DDQ
V
IH
V
IL
V
OH
V
OL
I
IL
I
OL
Min
3.0
2.0
-0.3
2.4
-
-5
-5
Typ
3.3
3.0
0
-
-
-
-
See Fig 1
Max
3.6
V
DD
+0.3
0.8
-
0.4
5
5
M32L1632512A
Unit
V
V
V
V
V
µ
Â
µ
Â
Note
Note 1
I
OH
= -2mA
I
OL
= 2mA
Note 2
Note 3
Note:
1. V
IL
(min) = -1.5V AC (pulse width
≤
5ns)
2. Any input 0V
≤
V
IN
≤
V
DD
+ 0.3V, all other pins are not under test = 0V.
4. Dout is disabled, 0V
≤
V
OUT
≤
V
DD
.
CAPACITANCE
(V
DD
/V
DDQ
= 3.3V, T
A
= 25
°
C , f = 1MH
Z
)
Parameter
Input capacitance (A0 ~ A10)
Input capacitance
(CLK, CKE, CS , RAS , CAS , WE , DSF& DQM0-3)
Data input/output capacitance (DQ0 ~ DQ31)
C
OUT
-
5
pF
Symbol
C
IN1
C
IN2
Min
-
-
Max
4
4
Unit
pF
pF
DECOUPLING CAPACITANCE GUIDE LINE
Recommended decoupling capacitance added to power line at board.
Parameter
Decoupling Capacitance between V
DD
& V
SS
Decoupling Capacitance between V
DDQ
& V
SSQ
Symbol
C
DC1
C
DC2
Value
0.1+0.01
0.1+0.01
Unit
uF
uF
*Note:
1. V
DD
and V
DDQ
pins are separated each other.
All V
DD
pins are connected in chip. All V
DDQ
pins are connected in chip.
2. V
SS
and V
SSQ
pins are separated each other.
All V
SS
pins are connected in chip. All V
SSQ
pins are connected in chip.
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jun. 2001
Revision
:
1.6
4/54
$ %
DC CHARACTERISTICS
Parameter
Symbol
Test Condition
Burst Length = 1
I
CC1
CAS
M32L1632512A
Recommended operating condition unless otherwise noted, T
A
= 0 to 70
°
C V
IH(min)
/V
IL(max)
=2.0V/0.8V
Version
Unit Note
Latency -5/5S -6/6S -7/7S -8/8S
Operating Current
(One Bank Active)
3
2
230
230
2
2
35
210
210
2
2
35
195
195
2
2
35
170
170
2
mA
2
35
mA
15
3
3
60
15
3
3
60
15
3
3
60
15
3
3
60
t
RC
≥
t
RC(min)
,
t
CC
≥
t
CC(min)
I
OL
= 0 mA
mA
1
I
CC2
P CKE
≤
V
IL(max)
,
t
CC
= 15ns
Precharge Standby Current
in power-down mode
I
CC2
PS CKE
≤
V
IL(max)
, CLK
≤
V
IL(max)
,
t
CC
=
∞
I
CC2
N CKE
≥
V
IH(min)
, CS
≥
V
IH(min)
,
t
CC
= 15ns
Precharge Standby Current
Input signals are changed one time during
in non power-down mode
30ns
I
CC2
NS CKE
≥
V
IH(min)
, CLK
≤
V
IL(max)
,
t
CC
=
∞
input signals are stable
Active Standby Current
in power-down mode
I
CC3
P CKE
≤
V
IL(max)
,
t
CC
= 15ns
I
CC3
PS CKE
≤
V
IL(min)
, CLK
≤
V
IL(max)
,
t
CC
=
∞
I
CC3
N CKE
≥
V
IH(min)
, CS
≥
V
IH(min)
,
t
CC
= 15ns
Input signals are changed one time during
30ns
I
CC3
NS CKE
≥
V
IH(min)
, CLK
≤
V
IL(max)
,
t
CC
=
∞
input signals are stable
Operating Current
(Burst Mode)
I
CC4
I
OL
= 0 mA, Page Burst
All Banks Activated,
t
CCD
=
t
CCD
(min)
mA
Active Standby Current
in non power-down mode
(One Bank Active)
mA
20
230
230
190
190
2
220
20
210
210
170
170
2
200
20
195
195
160
160
2
190
20
170
mA
1, 2
170
150
mA
3
150
2
180
mA
mA
4
3
2
Refresh Current
I
CC5
t
RC
≥
t
RC(min)
CKE
≤
0.2V
3
2
Self Refresh Current
Operating Current
(One Bank Block Write)
I
CC6
I
CC7
t
CC
≥
t
CC(min),
I
OL
= 0 mA,
t
BWC(min)
*Note : 1. Measured with outputs open.
2. Assumes minimum column address update cycle
t
CCD(min).
3. Refresh period is 32ms.
4. Assumes minimum column address update cycle
t
BWC(min).
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jun. 2001
Revision
:
1.6
5/54
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