ICE23
(L)M020
2 Megabit Mask ROM
General Description
The ICE23M020/ICE23LM020 is a high speed 2M bits CMOS mask ROM, with 256K X 8 bit data
structure.
Feature
1.
2.
3.
4.
5.
6.
7.
8.
90nS access time
256K x 8 bits
3.3V / 5V operating option
CMOS / TTL I/O option
CE / CEB select option
OE / OEB select option
Standby current : <5uA
32 Pin PDIP, SOP ,TSOP or PLCC Package.
Pin Definition
VDD
A12
A15
A16
A17
30
29
28
27
A14
A13
A8
A9
A11
OEB
A10
CEB
D7
26
25
24
23
22
21
14
15
16
17
18
19
20
D6
N/C
N/C
31
D5
N/C
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
VDD
N/C
A17
A7
A14
A6
A13
A5
A8
A4
8
9
10
11
12
13
A9
A3
A11
A2
OEB
A1
A10
A0
CEB
D0
D7
D6
7
6
5
4
3
2
1
32
32Pin PDIP
26
25
24
23
22
21
20
19
18
17
32-Lead PLCC
GND
D5
D1
D2
D4
D3
D3
Pin Assignments for 32-pin Plastic DIPs and 32-Lead PLCCs
1
ICE semiconductor, inc.
Rev.1.0 2003/2/20
D4
ICE23(L)M020
VDD
OEB
CEB
A17
A14
A13
A11
A10
N/C
A8
A9
D7
D6
D5
D4
18
15
32 31
30
29
28
27
26
25
24
23
22
21
20
19
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
A16
A15
A12
N/C
Pin Assignment of 32-Pin SOP
A11
A9
A8
A13
A14
A17
N/C
OEB
A10
CEB
D7
D6
D5
D4
VDD
N/C
A16
A15
A12
A7
A6
A5
A4
GND
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
D3
17
D3
GND
D2
D1
D0
A0
A1
A2
A3
Pin Assignment of 32-Pin TSOP
PIN DESCRIPTION
Name
VDD
GND
CE/CEB
OE/OEB
A0-17
DO0-7
I/O
P
P
I
I
I
O
Description
Positive power supply.
Negative power supply.
Chip enable input.
Output enable input.
Address input.
Data output.
ABSOLOUTE MAXIMUM RATINGS
Name
Supply Voltage
Input Voltage
Operating temperature
Storage temperature
Symbol
VDD
Vin
Topg
Tstg
2
Rating
-0.3 to +7.0
-0.5 to VDD +0.5
-20 to +70
-65 to +125
Unit
V
V
°C
°C
ICE semiconductor, inc.
Rev.1.0 2003/2/20
ICE23(L)M020
ALLOWABLE OPERATING CONDITIONS
Name
Supply Voltage 3.3V
Supply Voltage 5V
Input Voltage
Symbol
VDD
VDD
Vi
MIN
2.6
4.5
-0.3
TYP
3.3
5.0
MAX
3.6
5.5
VDD+0.3
Unit
V
V
V
DC ELECTRICAL CHARACTERISTICS
@VDD= 4.5~5.5V, T= -20~70°C, TTL
Item
Output high current
Output low current
Input high voltage
Input low voltage
Symbol
Ioh
Iol
Vih
Vil
Condition
Voh=VDD-0.5V
Vol=0.5V
-
-
MIN
-
2
2.2
-
MAX
-500
-
-
0.8
Unit
uA
mA
V
V
@VDD= 2.6~3.6V, T= -20~70°C, CMOS
Item
Output high current
Output low current
Input high voltage
Input low voltage
Symbol
Ioh
Iol
Vih
Vil
Condition
Voh=VDD-0.5V
Vol=0.5V
-
-
MIN
-
2
0.8xVDD
-
MAX
-2
-
-
0.2xVDD
Unit
mA
mA
V
V
AC ELECTRICAL CHARACTERISTICS
@VDD= 4.5~5.5V, T= -20~70°C, TTL
Vih / Vil = Min / Max, Tr = Tf = 10ns, Cl = 50pF
Item
Read cycle time
Address access time
Chip enable access time
Output enable access time
Output hold time from addresses change
OE disable to invalid output
Symbol
Trc
Taa
Tce
Toe
Toh
Toz
Tcz
MIN
90
-
-
-
0
0
0
MAX
-
90
90
40
-
20
20
Unit
ns
ns
ns
ns
ns
ns
ns
C
E disable to invalid output
3
ICE semiconductor, inc.
Rev.1.0 2003/2/20
ICE23(L)M020
@VDD= 2.6~3.6V, T= -20~70°C, CMOS
Vih / Vil = Min / Max, Tr = Tf = 10ns, Cl = 50pF
Item
Read cycle time
Address access time
Chip enable access time
Output enable access time
Output hold time from addresses change
OE disable to invalid output
Symbol
Trc
Taa
Tce
Toe
Toh
Toz
Tcz
MIN
120
-
-
-
0
0
0
MAX
-
120
120
40
-
20
20
Unit
ns
ns
ns
ns
ns
ns
ns
C
E disable to invalid output
T
RC
A[16:0]
T
C E
CEB
T
OEB
OE
T
AA
T
C Z
T
O Z
T
OH
D[7:0]
DATA VALID
DATA VALID
Figure 2: Read Cycle Timing diagram
4
ICE semiconductor, inc.
Rev.1.0 2003/2/20
ICE23(L)M020
PACKAGE INFORMATION
32-Pin PDIP
32
ITEM
A
B
C
D
E
F
G
H
I
J
K
L
M
MILLIMETERS
42.13max.
1.90[REF]
2.54[TP]
.46[TyP]
38.07
1.27[TyP]
3.30±.25
.51[REF]
3.94±.25
5.33max.
15.22±.25
13.97±.25
.25[TYP]
INCHES
1.660max
.075[REF]
.100[TP]
.018[TyP]
1.500
.050[TyP]
.130±.010
.020[REF]
.155±.010
.210max
.600±.010
.550±.010
.010[TYP]
17
1
A
16
K
L
I J
H
G
F
D
E
C
NOTE:
Each lead centerline is located within .25
mm[.01 inch] of its true position [TP] at
maximum matrial condtion.
B
M
0~15i
32-Pin SOP
32
ITEM
MILLIMETERS
INCHES
A
20.95max.
.825max
B
1.00[REF]
.039[REF]
C
1.27[TP]
.050[TP]
D
.40[TyP]
.016[TyP]
E
.05min.
.0002min.
F
3.05max.
.120max.
G
2.69±.13
.106±.005
H
14.12±.25
.556±.010
I
11.30±.13
.445±.005
J
1.42
.056
K
.20[TYP]
.008[TYP]
L
.79
.031
NOTE:
Each lead centerline is located within .25
mm[.01 inch] of its true position [TP] at
maximum matrial condtion.
17
1
A
16
H
I
F
J
G
K
E
B
L
D
C
32-Pin TSOP
ITEM
A
B
C
D
E
F
G
H
I
J
K
L
M
N
MILLIMETERS
20.0±.20
18.40±.10
8.20max.
.15[Typ.]
.80[Typ.]
.20±.10
.30±.10
.50[Typ.]
.45max.
0~.20
1.00±.10
1.27max.
.50
0~5
。
INCHES
.78±.006
.724±.004
.323max.
.006[Typ.]
.031[Typ.]
.008±.004
.012±.004
.020[TyP]
.018max.
0~.008
.039±.004
.050max
.020
.500
A
B
C
N
M
NOTE:
Each lead centerline is located within .25
mm[.01 inch] of its true position [TP]
D
at maximum material condition.
K
L
E
F
G
H
I
J
5
ICE semiconductor, inc.
Rev.1.0 2003/2/20
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