UTRON
Rev. 1.9
REVISION HISTORY
REVISION
Rev. 1.0
Rev. 1.1
Rev. 1.2
Rev. 1.3
Rev. 1.4
Rev. 1.5
Rev. 1.6
DESCRIPTION
UT62L1024
128KX8 BIT LOW POWER CMOS SRAM
Original
128Kx 8 Low Voltage CMOS SRAM
之
TN8106 body
已½
fine tunings,
將
I
SB1
降為
0.5uA(LL)
、
2uA(L)
、
Vcc range
：
3.0V~3.6V
Add STSOP-I Package
Modify the format of power consumption
Add speed : -55ns
Vcc min 3.1→2.7V
1. The symbols CE1# ,OE# & WE# are revised as CE1 , OE &
WE
2. Add Icc value of 55ns range(access time)
3. V
OH
is revised as 2.2V
4. I
SB1
is revised as 100µA
Revised 32 pin 8mmx13.4mm STSOP Package Outline Dimension
1. V
OH
is revised as 2.4V (min.)
2. Revised Package Outline Dimension
1. Add Operation temperature : Extended temp -20
℃
~80
℃
2. Add Order information for lead free product
DATE
Jun 01, 1997
Apr 05, 2000
Aug 29, 2000
Sep 01, 2000
Dec 01, 2000
Mar 15, 2001
Jun 26, 2001
Rev. 1.7
Rev. 1.8
Rev. 1.9
Nov 26, 2001
Apr 9, 2002
May 09.2003
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80033
UTRON
Rev. 1.9
UT62L1024
128KX8 BIT LOW POWER CMOS SRAM
GENERAL DESCRIPTION
The UT62L1024 is a 1,048,576-bit low power
CMOS static random access memory organized as
131,072 words by 8 bits. It is fabricated using high
performance, high reliability CMOS technology.
Easy memory expansion is provided by using two
chip enable inputs.( CE ,CE2) It is particularly well
suited for battery back-up nonvolatile memory
application.
The UT62L1024 operates from a single 2.7V~ 3.6V
power supply and all inputs and outputs are fully
TTL compatible.
FEATURES
Fast access time : 35/55/70ns (max.)
Low power consumption :
Operating current : 40/35/30mA (typical)
Standby current : 2.5µA (typical) L-version
0.5µA (typical) LL-version
Power supply range : 2.7V to 3.6V
Operating temperature :
Commercial : 0
℃
~70
℃
Extended : -20
℃
~80
℃
All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Data retention voltage : 2V (min.)
Package : 32-pin 600 mil PDIP
32-pin 450 mil SOP
32-pin 8x20 mm TSOP-1
32-pin 8x13.4 mm STSOP
FUNCTIONAL BLOCK DIAGRAM
1024 X 1024
MEMORY
ARRAY
A0-A16
DECODER
Vcc
Vss
I/O1-I/O8
I/O DATA
CIRCUIT
COLUMN I/O
CE
CE2
OE
CONTROL
CIRCUIT
WE
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80033
1
UTRON
Rev. 1.9
UT62L1024
128KX8 BIT LOW POWER CMOS SRAM
PIN CONFIGURATION
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A15
CE2
WE
A11
A9
A8
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
OE
A10
CE
I/O8
I/O7
I/O6
I/O5
I/O4
Vss
I/O3
I/O2
I/O1
A0
A1
A2
A3
A13
A8
A9
A11
OE
PDIP / SOP
PIN DESCRIPTION
SYMBOL
A0 - A16
I/O1 - I/O8
CE ,CE2
WE
OE
V
CC
V
SS
NC
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip enable 1,2 Inputs
Write Enable Input
Output Enable Input
Power Supply
Ground
No Connection
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
UT62L1024
WE
CE2
A15
Vcc
NC
A16
A14
A12
A7
A6
A5
A4
UT62L1024
25
24
23
22
21
20
19
18
17
A10
CE
I/O8
I/O7
I/O6
I/O5
I/O4
TSOP-I/STSOP
P80033
2
UTRON
Rev. 1.9
UT62L1024
128KX8 BIT LOW POWER CMOS SRAM
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Terminal Voltage with Respect to Vss
Operating Temperature
Commerical
Extended
Storage Temperature
Power Dissipation
DC Output Current
Soldering Temperature (under 10 sec)
SYMBOL
V
TERM
T
A
T
A
T
STG
P
D
I
OUT
T
solder
RATING
-0.5 to +4.6
0 to +70
-20 to +80
-65 to +150
1
50
260
UNIT
V
℃
℃
℃
W
mA
℃
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE
Standby
Standby
Output Disable
Read
Write
CE
H
X
L
L
L
CE2
X
L
H
H
H
OE
X
X
H
L
X
WE
X
X
H
H
L
I/O OPERATION
High - Z
High -Z
High - Z
D
OUT
D
IN
SUPPLY CURRENT
I
SB
,
I
SB1
I
SB
,
I
SB1
I
CC ,
I
CC1
I
CC ,
I
CC1
I
CC ,
I
CC1
Note: H = V
IH
, L=V
IL
, X = Don't care.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.7V~3.6V, T
A
= 0
℃
to +70
℃/
-20
℃
to +80
℃
(E))
PARAMETER
SYMBOL TEST CONDITION
*1
Input High Voltage
V
IH
*2
Input Low Voltage
V
IL
Input Leakage Current
I
IL
V
SS
≦
V
IN
≦
V
CC
Output Leakage Current I
OL
V
SS
≦
V
I/O
≦
V
CC
CE =V
IH
or CE2 = V
IL
or
Output High Voltage
Output Low Voltage
Average Operating
Power Supply Courrent
V
OH
V
OL
I
CC
OE
= V
IH
or
WE
= V
IL
I
OH
= - 1mA
I
OL
= 4mA
Cycle time =Min. 100% Duty,
CE =V
IL
, CE2 = V
IH
,
I
I/O
= 0mA
Cycle time = 1µs, 100% Duty,
CE
≦
0.2V,CE2
≧
V
CC
-0.2V,
I
I/O
= 0mA
CE =V
IH
or CE2 = V
IL
CE
≧
V
CC
-0.2V or
CE2
≦
0.2V
-L
-
LL
MIN.
2.0
- 0.5
-1
-1
2.4
-
-
-
-
-
-
-
-
TYP.
-
-
-
-
-
-
40
35
30
-
-
2.5
0.5
MAX.
V
CC
+0.5
0.6
1
1
-
0.4
60
50
40
5
1.0
100
4
20*
40
4
10*
UNIT
V
V
µA
µA
V
V
mA
mA
mA
mA
mA
µA
µA
35
55
70
I
CC1
Standby Power
Supply Current
I
SB
I
SB1
Notes:
1. Overshoot : Vcc+3.0v for pulse width less than 10ns.
2. Undershoot : Vss-3.0v for pulse width less than 10ns.
3. Overshoot and Undershoot are sampled, not 100% tested.
4. Those parameters are for reference only under 50
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80033
3
UTRON
Rev. 1.9
UT62L1024
128KX8 BIT LOW POWER CMOS SRAM
CAPACITANCE
(T
A
=25
℃
, f=1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
C
IN
C
I/O
MIN.
-
-
MAX.
6
8
UNIT
pF
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0.4V to 2.4V
5ns
1.5V
C
L
=50pF, I
OH
/I
OL
=-1mA/2mA
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.7V~3.6V , T
A
= 0
℃
to +70
℃/
-20
℃
to +80
℃
(E))
(1) READ CYCLE
PARAMETER
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low-Z
Output Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
(2) WRITE CYCLE
PARAMETER
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write-Time
Output Active from End of Write
Write to Output in High-Z
SYMBOL
t
WC
t
AW
t
CW
t
AS
t
WP
t
WR
t
DW
t
DH
t
OW
*
t
WHZ
*
UT62L1024-35
UT62L1024-55
UT62L1024-70
UT62L1024-35
UT62L1024-55
UT62L1024-70
SYMBOL
t
RC
t
AA
t
ACE
t
OE
t
CLZ
*
t
OLZ
*
t
CHZ
*
t
OHZ
*
t
OH
MIN.
35
-
-
-
10
5
-
-
5
MAX.
-
35
35
25
-
-
25
25
-
MIN.
55
-
-
-
10
5
-
-
5
MAX.
-
55
55
30
-
-
30
30
-
MIN.
70
-
-
-
10
5
-
-
5
MAX.
-
70
70
35
-
-
35
35
-
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
MIN.
35
30
30
0
25
0
20
0
5
-
MAX.
-
-
-
-
-
-
-
-
-
15
MIN.
55
50
50
0
40
0
25
0
5
-
MAX. MIN.
-
70
-
60
-
60
-
0
-
45
-
0
-
30
-
0
-
5
20
-
MAX.
-
-
-
-
-
-
-
-
-
25
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*These parameters are guaranteed by device characterization, but not production tested.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80033
4
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