UTRON
Rev. 1.4
UT62L5128
512K X 8 BIT LOW POWER CMOS SRAM
REVISION HISTORY
REVISION
Preliminary Rev. 0.5
Rev. 1.0
Released DATE
Mar, 2001
Jun 21,2001
1. The symbols CE# and OE# and WE# are revised as. CE and
OE and
WE
.
2. Separate Industrial and Consumer SPEC.
3. Add access time 55ns range.
Aug 3,2001
Add STSOP package
Mar 25,2002
Add SOP package
1. Revised 36-pin TFBGA package outline dimension：
a、 Rev. 1.2 : ball diameter=0.3mm
May 3,2002
b、 Rev. 1.3 : ball diameter=0.35mm
2. Revised DC ELECTRICAL CHARACTERISTICS：
c、 Revised V
IH
as 2.2V
1. Revised Operation surrent :
-Icc(max) 45/35/25mA 40/30/25mA
-Icc(Typ) 30/25/20mA 30/20/16mA
2. Revised Standby current : 20/3uA 20/2uA
3. Revised V
OH
(Typ) : NA 2.7V
May 8,2003
4. Add V
IH
(max)=V
CC
+2.0V for pulse width less than 10ns.
V
IL
(min)=V
SS
-2.0V for pulse width less than 10ns.
5. Revised AC Table t
OHZ*
characteristics
6. Add order information for lead free product
DESCRIPTION
Original.
Rev. 1.1
Rev. 1.2
Rev. 1.3
Rev. 1.4
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80051
1
UTRON
Rev. 1.4
UT62L5128
512K X 8 BIT LOW POWER CMOS SRAM
GENERAL DESCRIPTION
The UT62L5128 is a 4,194,304-bit low power CMOS
static random access memory organized as 524,288
words by 8 bits. It is fabricated using high performance,
high reliability CMOS technology.
The UT62L5128 operates from a wide range
2.7V~3.6V power supply and supports extended
operating temperature range.
The UT62L5128 is designed for high density and low
power memory applications. The device has a data
retention mode that guarantees data to remain valid at
a minimum power supply voltage of 1.5V.
FEATURES
Fast Access time : 55/70/100ns
CMOS Low power operating
Operating current : 40/30/25mA (Icc max.)
Standby current : 20µA (typ.) L-version
2µA (typ.) LL-version
Single 2.7V~3.6V power supply
Operating Temperature :
Commercial : 0
℃
~70
℃
Extended : -20
℃
~80
℃
All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Data retention voltage : 1.5V (min)
Package : 32-pin 450 mil SOP
32-pin 8mm × 20mm TSOP-
Ⅰ
32-pin 8mm × 13.4mm STSOP
36-pin 6mm × 8mm TFBGA
FUNCTIONAL BLOCK DIAGRAM
512K
×
8
MEMORY
ARRAY
A0-A18
DECODER
Vcc
Vss
I/O1-I/O8
I/O DATA
CIRCUIT
COLUMN I/O
CE
OE
WE
CONTROL
CIRCUIT
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80051
2
UTRON
Rev. 1.4
UT62L5128
512K X 8 BIT LOW POWER CMOS SRAM
PIN CONFIGURATION
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A15
A17
WE
A13
A8
A9
A11
OE
A10
CE
I/O8
I/O7
I/O6
I/O5
I/O4
A
B
C
D
E
F
G
H
A0
I/O5
I/O6
Vss
Vcc
I/O7
I/O8
A9
A1
A2
NC
WE
NC
A3
A4
A5
A6
A7
A8
I/O1
I/O2
Vcc
Vss
A17
OE
A10
CE
A11
A18
A16
A12
A15
A13
I/O3
I/O4
A14
SOP
1
2
3
4
5
6
TFBGA
A11
A9
A8
A13
WE
A17
A15
Vcc
A18
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
I/O8
I/O7
I/O6
I/O5
I/O4
Vss
I/O3
I/O2
I/O1
A0
A1
A2
A3
PIN DESCRIPTION
SYMBOL
A0 - A18
I/O1 - I/O8
CE
WE
OE
Vcc
Vss
NC
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Write Enable Input
Output Enable Input
Power Supply
Ground
No Connection
TSOP-1 / STSOP
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80051
3
UTRON
Rev. 1.4
UT62L5128
512K X 8 BIT LOW POWER CMOS SRAM
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Terminal Voltage with Respect to V
SS
Commercial
Operating Temperature
Extended
Storage Temperature
Power Dissipation
DC Output Current
Soldering Temperature (under 10 secs)
SYMBOL
V
TERM
T
A
T
A
T
STG
P
D
I
OUT
Tsolder
RATING
-0.5 to 4.6
0 to 70
-20 to 80
-65 to 150
1
50
260
UNIT
V
℃
℃
℃
W
mA
℃
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE
Standby
Output Disable
Read
Write
Note:
WE
X
H
H
L
CE
H
L
L
L
OE
X
H
L
X
I/O OPERATION
High – Z
High – Z
D
OUT
D
IN
SUPPLY CURRENT
I
SB
, I
SB1
I
CC
, I
CC1
, I
CC2
I
CC
, I
CC1
, I
CC2
I
CC
, I
CC1
, I
CC2
H = V
IH
, L=V
IL
, X = Don't care.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.7V~3.6V, T
A
=0
℃
to 70
℃
/ -20
℃
to 80
℃
(E))
PARAMETER
Power Voltage
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Operating Power
Supply Current
SYMBOL
V
CC
*1
V
IH
＊
2
V
IL
I
LI
I
LO
V
OH
V
OL
I
CC
TEST CONDITION
MIN.
2.7
2.2
- 0.2
-1
-1
2.2
-
-
-
-
-
-
-
-L
-LL
-
-
TYP.
3.0
-
-
-
-
2.7
-
30
20
16
4
8
0.3
20
2
MAX. UNIT
3.6
V
Vcc+0.3
V
0.6
V
1
µA
1
µA
-
V
0.4
V
40
mA
30
mA
25
mA
5
10
0.5
80
20
mA
mA
mA
µA
µA
V
SS
≦
V
IN
≦
V
CC
V
SS
≦
V
I/O
≦
V
CC,
Output Disable
I
OH
= - 1mA
I
OL
= 2.1mA
Cycle time=Min,100% duty
I
I/O
=0mA ,
CE
= V
IL
100% duty, I
I/O=
0mA,
CE
≦
0.2,
other pins at 0.2V or Vcc-0.2V
55
70
100
TCycle=
1µs
Tcycle=
500ns
Average Operating
Current
Standby Current(TTL)
Standby Current(CMOS)
Icc1
Icc2
I
SB1
I
SB1
CE
=V
IH
,other pins = V
IH
or V
IL
CE
≧
V
CC
-0.2V
other pins at 0.2V or Vcc-0.2V
Notes:
1. Overshoot : Vcc+2.0v for pulse width less than 10ns.
2. Undershoot : Vss-2.0v for pulse width less than 10ns.
3. Overshoot and Undershoot are sampled, not 100% tested.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80051
4
UTRON
Rev. 1.4
UT62L5128
512K X 8 BIT LOW POWER CMOS SRAM
CAPACITANCE
(T
A
=25
℃
, f=1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
C
IN
C
I/O
MIN.
-
-
MAX
6
8
UNIT
pF
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0V to 3.0V
5ns
1.5V
C
L
= 30pF+1TTL, I
OH
/I
OL
= -1mA/2.1mA
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.7V~3.6V , T
A
=0
℃
to 70
℃
/ -20
℃
to 80
℃
(E))
(1) READ CYCLE
PARAMETER
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
SYMBOL
t
RC
t
AA
t
ACE
t
OE
t
CLZ*
t
OLZ*
t
CHZ*
t
OHZ*
t
OH
UT62L5128-55
MIN.
MAX.
55
-
-
55
-
55
-
30
10
-
5
-
-
20
-
20
10
-
UT62L5128-70
MIN.
MAX.
70
-
-
70
-
70
-
35
10
-
5
-
-
25
-
25
10
-
UT62L5128-100
MIN.
MAX.
100
-
-
100
-
100
-
50
10
-
5
-
-
30
-
30
10
-
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
(2) WRITE CYCLE
PARAMETER
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High Z
SYMBOL
t
WC
t
AW
t
CW
t
AS
t
WP
t
WR
t
DW
t
DH
t
OW*
t
WHZ*
UT62L5128-55
MIN.
MAX.
55
-
50
-
50
-
0
-
45
-
0
-
25
-
0
-
5
-
-
30
UT62L5128-70
MIN.
MAX.
70
-
60
-
60
-
0
-
55
-
0
-
30
-
0
-
5
-
-
30
UT62L5128-100
MIN.
MAX.
100
-
80
-
80
-
0
-
70
-
0
-
40
-
0
-
5
-
-
40
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*These parameters are guaranteed by device characterization, but not production tested.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80051
5
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