$ %
DRAM
FEATURES
y
y
y
y
M11B16161A / M11B16161SA
M11L16161A / M11L16161SA
1M x 16 DRAM
EDO PAGE MODE
ORDERING INFORMATION - PACKAGE
42-pin 400mil SOJ
44 / 50-pin 400mil TSOP (TypeII)
PRODUCT NO.
M11B16161A-45J/50J/60J
M11B16161SA-45J/50J/60J
M11L16161A-45J/50J/60J
M11L16161SA-45J/50J/60J
M11B16161A-45T/50T/60T
M11B16161SA-45T/50T/60T
M11L16161A-45T/50T/60T
Refresh Vcc
Normal
*Self-
Refresh
Normal
Self-
Refresh
Normal
*Self-
Refresh
Normal
3.3V
5V
TSOPII
3.3V
5V
SOJ
PACKING
TYPE
y
y
y
y
y
y
X16 organization
EDO (Extended Data-Out) access mode
2
CAS
Byte/Word Read/Write operation
Single power supply :
5V
±
10% Vcc for 5V product
3.3V
±
10% Vcc for 3.3V product
Interface for inputs and outputs
TTL-compatible for 5V products
LVTTL-compatible for 3.3V products
1024-cycle refresh in 16ms
Refresh modes :
RAS
only,
CAS
BEFORE
RAS
(CBR)
and HIDDEN capabilities,
Optional self-Refresh capabilities(S-ver. Only)
JEDEC standard pinout
Key AC Parameter
-45
-50
-60
t
RAC
45
50
60
t
CAC
11
13
15
t
RC
77
84
104
t
PC
16
20
25
M11L16161SA-45T/50T/60T Self-
Refresh
* Ordered by special request
GENERAL DESCRIPTION
The M11B16161/M11L16161 series is a randomly accessed solid state memory, organized as 1,048,576 x 16 bits device. It
offers Extended Data-Output access mode. Single power supply (5V
±
10%, 3.3V
±
10%), access time (-45,-50,-60), self-
refresh function and package type (SOJ, TSOP II) are optional features of this family. All these family have
CAS
- before -
RAS
,
RAS
-only refresh and Hidden refresh.
Two access modes are supported by this device : Byte access and Word access. Use only one of the two
CAS
and leave
the other staying high will result in a BYTE access. WORD access happens when two
CAS
(
CASL
,
CASH
) are used.
CASL
transiting low during READ or WRITE cycle will output or input data into the lower byte (IO0~IO7), and
CASH
transiting low will
output or input data into the upper byte (IO8~15).
PIN ASSIGNMENT
SOJ Top View
V
CC
I/O0
I/O1
I/O2
I/O3
V
CC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RA S
NC
NC
A0
A1
A2
A3
V
C C
TSOP (TypeII) Top View
V
SS
I/O15
I/O14
I/O13
I/O12
V
SS
I/O11
I/O10
I/O9
I/O8
NC
CASL
CA S H
OE
A9
A8
A7
A6
A5
A4
V
S S
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
V
CC
V
CC
I/O 0
I/O 1
I/O 2
I/O 3
V
CC
I/O 4
I/O 5
I/O 6
I/O 7
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
V
SS
I/O1 5
I/O1 4
I/O1 3
I/O1 2
V
SS
I/O1 1
I/O1 0
I/O 9
I/O 8
NC
NC
CA SL
CASH
OE
A9
A8
A7
A6
A5
A4
V
S S
Elite Semiconductor Memory Technology Inc.
Publication Date
:
May. 2001
Revision
:
1.3
1/16
$ %
FUNCTIONAL BLOCK DIAGRAM
WE
RAS
CASL
CASH
CONTROL
LOGIC
M11B16161A / M11B16161SA
M11L16161A / M11L16161SA
DATA-IN BUFFER
16
IO0
:
IO15
CLOCK
GENERATOR
DATA-OUT
BUFFER
COLUMN
10
DECODER
1024
16
OE
16
10
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
10
COLUMN
ADDRESS
BUFFER
REFRESH
CONTROLER
SENSE AMPLIFIERS
I/O GATING
8
1024 x 16
REFRESH
COUNTER
10
ROW.
ADDRESS
BUFFERS(10)
10
ROW
DECODER
1024
1024 x 1024 x 16
MEMORY
ARRAY
V
CC
V
BB
GENERATOR
V
SS
PIN DESCRIPTIONS
PIN NO.
(SOJ Package)
17~20, 23~28
14
30
31
13
29
2~5,7~10,33~36,38~41
1,6,21
22,37,42
11,12,15,16,32
PIN NAME
TYPE
DESCRIPTION
Address Input
Row Address : A0~A9
Column Address : A0~A9
Row Address Strobe
Column Address Strobe / Upper Byte Control
Column Address Strobe / Lower Byte Control
Write Enable
Output Enable
Data Input / Output
Power, (5V or 3.3V)
Ground
No Connect
A0~A9
RAS
CASH
CASL
WE
OE
Input
Input
Input
Input
Input
Input
Input / Output
Supply
Ground
-
I/O0 ~ I/O15
V
CC
V
SS
NC
Elite Semiconductor Memory Technology Inc.
Publication Date
:
May. 2001
Revision
:
1.3
2/16
$ %
ABSOLUTE MAXIMUM RATINGS
Voltage on Any pin Relative to Vss
5V Product
… ……-1V to +7V
3.3V Product
… ……-0.5V to +4.6V
Operating Temperature, T
A
(ambient) ….0
°
C to +70
°
C
Storage Temperature (plastic) ……….-55
°
C to +150
°
C
Power Dissipation …………………………………1.0W
Short Circuit Output Current ……………………50mA
M11B16161A / M11B16161SA
M11L16161A / M11L16161SA
Permanent device damage may occur if “Absolute
Maximum Ratings” are exceeded. This is a stress rating
only, and functional operation of the device above those
conditions indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED
OPERATING CONDITIONS
(0
°
C
≤
T
A
≤
70
°
C )
PARAMETER
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
0V
≤
V
IN
≤
V
IH(max)
0V
≤
V
OUT
≤
V
CC
Output(s) disable
5V
I
OH
= -5 mA
3.3V I
OH
= -2 mA
5V
I
OL
= 4.2 mA
3.3V I
OL
= 2 mA
CONDITIONS
SYMBOL
MIN
V
CC
V
SS
V
IH
V
IL
I
LI
I
LO
V
OH
V
OL
3.0
0
2.0
-1.0
-10
-10
2.4
-
3.3V
MAX
3.6
0
V
CC
+0.3
0.8
10
10
-
0.4
MIN
4.5
0
2.4
-1.0
-10
-10
2.4
-
5V
MAX
5.5
0
V
CC
+0.3
0.8
10
10
-
0.4
V
V
V
V
µ
A
µ
A
V
V
1
1
1
UNITS NOTES
Note : 1.All Voltages referenced to V
SS
MAX
-45
150
4
2
I
CC3
I
CC4
I
CC6
I
CC7
I
CC8
150
150
150
500
500
-50
140
4
2
140
140
140
500
500
-60
130
4
2
130
130
130
500
500
PARAMETER
Operating Current
Standby Current
CONDITIONS
RAS
,
CAS
cycling , t
RC
=min
SYMBOL
I
CC1
I
CC2
UNITS NOTES
mA
mA
mA
mA
mA
mA
µ
A
µ
A
2
1,3
1,2
TTL interface ,
RAS
,
CAS
= V
IH
,
D
OUT
=High-Z
CMOS interface,
RAS
,
CAS
≥
V
CC
-0.2V
RAS
only refresh Current
t
RC
= min
t
PC
= min
t
RC
= min
Standby with CBR refresh, t
RC
= 62.4us
t
RAS
≤
300ns, D
OUT
=Hi-Z, CMOS interface
RAS
,
CAS
≤
0.2V, D
OUT
=Hi-Z, CMOS
interface
EDO Page Mode Current
CAS
Before
RAS
Refresh
Current
Battery Backup Current
(S-ver. Only)
Self Refresh Current
(S-ver. Only)
Note
:
1. I
CC
max is specified at the output open condition.
2. Address can be changed twice or less while
RAS
=V
IL .
3. Address can be changed once or less while
CAS
=V
IH
.
Elite Semiconductor Memory Technology Inc.
Publication Date
:
May. 2001
Revision
:
1.3
3/16
$ %
CAPACITANCE
(Ta = 25
°
C , V
CC
= 5V
±
10% or 3.3V
±
10%)
PARAMETER
Input Capacitance (address)
Input Capacitance (
RAS
,
CASH
,
CASL
,
WE
,
OE
)
Output capacitance (I/O0~I/O15)
SYMBOL
C
I1
C
I2
C
I / O
TYP
-
-
-
M11B16161A / M11B16161SA
M11L16161A / M11L16161SA
MAX
5
7
10
UNIT
pF
pF
pF
AC ELECTRICAL CHARACTERISTICS
(Ta = 0 to 70
°
C , V
CC
=5V
±
10% or 3.3V
±
10%, V
SS
= 0V) (note 14)
Test Conditions
Input timing reference levels : 0.8V, 2.4V (for 5V power supply), 0.8V, 2.0V (for 3.3V power supply)
Output reference level : V
OL
= 0.8V, V
OH
=2.0V
Output Load : 2TTL gate + CL (50pF)
Assumed t
T
= 2ns
PARAMETER
Read or Write Cycle Time
Read Write Cycle Time
EDO-Page-Mode Read or Write Cycle
Time
EDO-Page-Mode Read-Write Cycle
Time
Access Time From
RAS
Access Time From
CAS
Access Time From
OE
Access Time From Column Address
Access Time From
CAS
Precharge
RAS
Pulse Width
RAS
Pulse Width (EDO Page Mode)
RAS
Hold Time
RAS
Precharge Time
CAS
Pulse Width
CAS
Hold Time
CAS
Precharge Time
RAS
to
CAS
Delay Time
CAS
to
RAS
Precharge Time
SYMBOL
t
RC
t
RWC
t
PC
t
PCM
t
RAC
t
CAC
t
OAC
t
AA
t
ACP
t
RAS
t
RASC
t
RSH
t
RP
t
CAS
t
CSH
t
CP
t
RCD
t
CRP
t
ASR
t
RAH
t
RAD
t
ASC
t
CAH
t
AR
t
RAL
t
ACH
-45
MIN
77
97
16
53
45
11
11
22
25
45
45
6
28
6
35
6
10
5
0
6
8
0
6
40
23
10
23
34
10,000
10,000
100,000
50
50
7
30
7
37
7
11
5
0
7
9
0
7
44
25
11
MAX
MIN
84
110
20
58
-50
MAX
MIN
104
135
25
68
50
13
13
25
28
10,000
100,000
60
60
10
40
10,000
10
40
10
37
14
5
0
10
25
12
0
10
55
30
13
-60
MAX
UNIT Notes
ns
ns
ns
ns
22
22
4
5,20
13,20
20
60
15
15
30
33
10,000
100,000
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
10,000
ns
ns
ns
24
19
6,23
7,18
19
45
ns
ns
ns
ns
Row Address Setup Time
Row Address Hold Time
RAS
to Column Address Delay Time
30
ns
ns
ns
ns
ns
ns
8
18
18
Column Address Setup Time
Column Address Hold Time
Column Address Hold Time (Reference
to
RAS
)
Column Address to
RAS
Lead Time
Column Address setup to
CAS
precharge
Elite Semiconductor Memory Technology Inc.
Publication Date
:
May. 2001
Revision
:
1.3
4/16
$ %
(Continued)
-45
PARAMETER
Read Command Setup Time
Read Command Hold Time Reference to
CAS
Read Command Hold Time Reference to
RAS
CAS
to Output in Low-Z
M11B16161A / M11B16161SA
M11L16161A / M11L16161SA
-50
MIN
MAX
-60
MIN
MAX
UNIT
Notes
SYMBOL
t
RCS
t
RCH
t
RRH
t
CLZ
t
OFF1
t
OFF2
t
WCS
t
WCH
t
WCR
t
WP
t
RWL
t
CWL
t
DS
t
DH
t
DHR
t
RWD
t
AWD
t
CWD
t
T
t
REF
t
REF
t
RPC
t
CSR
t
CHR
t
OEH
t
OES
t
OEHC
t
OEP
t
ORD
t
CLCH
t
COH
t
WHZ
t
RASS
t
RPS
t
CHS
t
RSR
t
RHR
MIN
MAX
0
0
0
0
0
0
0
6
40
6
11
6
0
6
40
57
34
23
1
50
16
64
11
11
0
0
0
0
0
0
0
7
44
7
13
7
0
7
44
67
42
30
1
50
16
64
13
13
0
0
0
0
0
0
0
10
55
10
15
10
0
10
55
79
49
34
1
50
16
64
15
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
ns
us
ns
ns
ns
ns
15,18
9,15,19
9
20
10,17,20
17,26
11,15,18
15,25
15
15
15
15,19
12,20
12,20
11
11
11,18
2,3
Output Buffer Turn-off Delay From
CAS
or
RAS
Output Buffer Turn-off to
OE
Write Command Setup Time
Write Command Hold Time
Write Command Hold Time(Reference to
RAS
)
Write Command Pulse Width
Write Command to
RAS
Lead Time
Write Command to
CAS
Lead Time
Data-in Setup Time
Data-in Hold Time
Data-in Hold Time (Reference to
RAS
)
RAS
to
WE
Delay Time
Column Address to
WE
Delay Time
CAS
to
WE
Delay Time
Transition Time (rise or fall)
Refresh Period (1024 cycles)
Refresh Period (1024 cycles) Self Refresh
RAS
to
CAS
Precharge Time
CAS
Setup Time(CBR REFRESH)
CAS
Hold Time(CBR REFRESH)
OE
Hold Time From
WE
During Read-Mode-Write
Cycle
OE
Low to
CAS
High Setup Time
OE
High Hold Time From
CAS
High
OE
Precharge Time
OE
Setup Prior to
RAS
During Hidden Refresh
Cycle
5
5
10
6
5
2
2
0
6
3
0
100
77
-50
0
6
11
5
5
10
7
5
2
2
0
7
3
0
100
84
-50
0
7
13
5
5
10
10
5
2
2
0
10
3
0
100
104
-50
0
10
1,18
1,19
16
Last
CAS
Going Low to First
CAS
Returning High
Data Output Hold After
CAS
Returning Low
Output Disable Delay From
WE
Self Refresh
RAS
Low Pulse width
Self Refresh
RAS
High Precharge Time
Self Refresh
CAS
Hold Time
Read Setup Time Reference to
RAS
in CBR/SR
Read Hold Time Reference to
RAS
in CBR/SR
21
27,28
27,28
27,28
27,28
27,28
Elite Semiconductor Memory Technology Inc.
Publication Date
:
May. 2001
Revision
:
1.3
5/16
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