UTRON
Rev. 1.1
UT62L1024(I)
128K X 8 BIT LOW POWER CMOS SRAM
REVISION HISTORY
REVISION
Rev. 1.0
Rev. 1.1
DESCRIPTION
Original.
Add order information for lead free product
Date
Mar. 27. 2003
May. 09. 2003
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80078
1
UTRON
Rev. 1.1
UT62L1024(I)
128K X 8 BIT LOW POWER CMOS SRAM
GENERAL DESCRIPTION
The UT62L1024(I) is a 1,048,576-bit low power
CMOS static random access memory organized as
131,072 words by 8 bits. It is fabricated using high
performance, high reliability CMOS technology.
The UT62L1024(I) is designed for very low power
system applications. It is particularly well suited for
battery back-up nonvolatile memory applications.
It operates from a wide range of 2.5V~ 3.6V supply
voltage. Easy memory expansion is provided by
using two chip enable input, CE & CE2. And all
inputs and three-state outputs are fully TTL
compatible.
FEATURES
Fast access time : 55/70ns
CMOS low power operation
Operating current : 20/18/15mA (TYP.)
Standby current : 20 uA(TYP.) L -version
2 uA(TYP.) LL-version
Single 2.5V~3.6V power supply
Operating temperature:
Industrial : -40
℃
~85
℃
All TTL compatible inputs and outputs
Fully static operation
Three state outputs
Data retention voltage: 1.5V (min)
Package : 32-pin 450mil SOP
32-pin 8mm x 20mm TSOP-
Ⅰ
32-pin 8mm x 13.4mm STSOP
36-pin 6mm × 8mm TFBGA
FUNCTIONAL BLOCK DIAGRAM
A0-A16
DECODER
2048 x 512
MEMORY
ARRAY
Vcc
Vss
I/O1-I/O8
I/O DATA
CIRCUIT
COLUMN I/O
CE
CE2
OE
WE
CONTROL
CIRCUIT
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80078
2
UTRON
Rev. 1.1
UT62L1024(I)
128K X 8 BIT LOW POWER CMOS SRAM
PIN CONFIGURATION
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/ O 1
I/ O 2
I/ O 3
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE
I/ O 8
I/ O 7
I/ O 6
I/ O 5
I/ O 4
A
B
C
D
E
F
G
H
A0
I/O 5
I/O 6
V ss
V cc
I/O 7
I/O 8
A9
A1
A2
CE2
A3
A4
A5
A6
A7
A8
I/O 1
I/O 2
V cc
V ss
SOP
UT62L1024(I)
WE
NC
NC
OE
CE
NC
A 16
A 12
A 15
A 13
I/O 3
I/O 4
A 14
A 10 A 11
1
2
3
4
5
6
TFBGA
A11
A9
A8
A13
WE
CE2
A15
Vcc
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
UT62L1024(I)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
I/O8
I/O7
I/O6
I/O5
I/O4
Vss
I/O3
I/O2
I/O1
A0
A1
A2
A3
TSOP-1/STSOP
PIN DESCRIPTION
SYMBOL
A0 - A16
I/O1 - I/O8
CE ,CE2
WE
OE
V
CC
V
SS
NC
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Enable Inputs
Write Enable Input
Output Enable Input
Power Supply
Ground
No Connection
P80078
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
3
UTRON
Rev. 1.1
UT62L1024(I)
128K X 8 BIT LOW POWER CMOS SRAM
TRUTH TABLE
MODE
Standby
Output Disable
Read
Write
Note:
CE
H
X
L
L
L
CE2
X
L
H
H
H
OE
X
X
H
L
X
WE
X
X
H
H
L
I/O OPERATION SUPPLY CURRENT
High - Z
High - Z
High - Z
D
OUT
D
IN
I
SB
,
I
SB1
I
SB
,
I
SB1
I
CC
,
I
CC1,
I
CC2
I
CC
,
I
CC1,
I
CC2
I
CC
,
I
CC1,
I
CC2
H = V
IH
, L=V
IL
, X = Don't care.
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Terminal Voltage with Respect to V
SS
Operating Temperature
Industrial
Storage Temperature
Power Dissipation
DC Output Current
Soldering Temperature (under 10 secs)
SYMBOL
V
TERM
T
A
T
STG
P
D
I
OUT
Tsolder
RATING
-0.5 to 4.6
-40 to 85
-65 to 150
1
50
260
UNIT
V
℃
℃
W
mA
℃
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device
reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.5V~3.6V, T
A
= -40
℃
to 85
℃
)
PARAMETER
Power Voltage
SYMBOL
TEST CONDITION
V
CC
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
V
IH
＊
2
V
IL
I
LI
I
LO
V
OH
V
OL
I
CC
＊
1
MIN. TYP. MAX. UNIT
2.5 3.0
3.6
V
2.2
-
Vcc+0.3 V
- 0.2
-
0.6
V
-1
-
1
V
SS
≦
V
IN
≦
V
CC
µA
-1
-
1
V
SS
≦
V
I/O
≦
V
CC,
Output Disabled
µA
-
V
I
OH
= - 1mA (I
OH
= -0.5mA when Vcc<2.7V)
2.2 2.7
-
-
0.4
V
I
OL
= 2.1mA
Cycle time=Min.100% duty,
55
70
-
-
-
-
20
18
4
8
0.3
20
2
35
30
5
10
0.5
80
10
mA
mA
mA
mA
mA
µA
µA
CE
=V
IL
and CE2 = V
IH
,
I
I/O
=0mA
Operating Current
I
CC1
I
CC2
100%duty, I
I/O=
0mA,
CE
≦
0.2V TCycle=
1µs
and CE2
≧
Vcc-0.2V, other pins
TCycle=
at 0.2V or Vcc-0.2V
500ns
Standby Current (TTL)
Standby Current (CMOS)
I
SB
I
SB1
CE
=V
IH
or CE2 = V
IL
CE
=V
CC
-0.2V or CE2=0.2V,
other pins at 0.2V or Vcc-0.2V
-L
-LL
-
-
-
Notes:
1. Overshoot : Vcc+3.0v for pulse width less than 10ns.
2. Undershoot : Vss-3.0v for pulse width less than 10ns.
3. Overshoot and Undershoot are sampled, not 100% tested.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80078
4
UTRON
Rev. 1.1
UT62L1024(I)
128K X 8 BIT LOW POWER CMOS SRAM
CAPACITANCE
(T
A
=25
℃
, f=1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
C
IN
C
I/O
MIN.
-
-
MAX
6
8
UNIT
pF
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0.1V
CC
to 0.9V
CC
5ns
1.5V
C
L
= 30pF+1TTL, I
OH
= -1mA, I
OL
= 2.1mA
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.5V~3.6V, T
A
= - 40
℃
to 85
℃
)
(1) READ CYCLE
PARAMETER
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
SYMBOL
t
RC
t
AA
t
ACE
t
OE
t
CLZ*
t
OLZ*
t
CHZ*
t
OHZ*
t
OH
UT62L1024(I)-55
MIN.
MAX.
55
-
-
55
-
55
-
30
10
-
5
-
-
20
-
20
10
-
UT62L1024(I)-70
MIN.
MAX.
70
-
-
70
-
70
-
35
10
-
5
-
-
25
-
25
10
-
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
(2) WRITE CYCLE
PARAMETER
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High Z
SYMBOL
t
WC
t
AW
t
CW
t
AS
t
WP
t
WR
t
DW
t
DH
t
OW*
t
WHZ*
UT62L1024(I)-55
MIN.
MAX.
55
-
50
-
50
-
0
-
45
-
0
-
25
-
0
-
5
-
-
20
UT62L1024(I)-70
MIN.
MAX.
70
-
60
-
60
-
0
-
55
-
0
-
30
-
0
-
5
-
-
25
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*These parameters are guaranteed by device characterization, but not production tested.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80078
5
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