ESMT
Flash
F25L64QA
64 Mbit Serial Flash Memory
with Dual and Quad
FEATURES
Single supply voltage 2.65~3.6V
Standard, Dual and Quad SPI
Speed
- Read max frequency: 50MHz
- Fast Read max frequency: 50MHz / 86MHz / 104MHz
- Fast Read Dual/Quad max frequency: 50MHz / 86MHz /
104MHz
(100MHz / 172MHz / 208MHz equivalent Dual SPI;
200MHz / 344MHz / 416MHz equivalent Quad SPI)
Low power consumption
- Active current: 25 mA (max.)
- Standby current: 25
μ
A (max.)
- Deep Power Down current: 10
μ
A (max.)
Reliability
- 100,000 typical program/erase cycles
- 20 years Data Retention
Program
- Page programming time: 1.5 ms (typical)
Erase
- Chip Erase time 35 sec (typical)
- 64K bytes Block Erase time 1 sec (typical)
- 32K bytes Block Erase time 500 ms (typical)
- 4K bytes Sector Erase time 120 ms (typical)
Page Programming
- 256 byte per programmable page
Program / Erase Suspend and Resume
Lockable 512 bytes OTP security sector
SPI Serial Interface
- SPI Compatible: Mode 0 and Mode 3
End of program or erase detection
Write Protect (
WP
)
Hold Pin ( HOLD )
All Pb-free products are RoHS-Compliant
ORDERING INFORMATION
Product ID
F25L64QA –50PAG
F25L64QA –86PAG
F25L64QA –100PAG
F25L64QA –50PHG
F25L64QA –86PHG
F25L64QA –100PHG
F25L64QA –50HG
F25L64QA –86HG
F25L64QA –100HG
F25L64QA –50VAG
F25L64QA –86VAG
F25L64QA –100VAG
Speed
50MHz
86MHz
104MHz
50MHz
86MHz
104MHz
50MHz
86MHz
104MHz
50MHz
86MHz
104MHz
8-lead
VSOP
208mil
Pb-free
8-contact
WSON
6x5 mm
Pb-free
16-lead
SOIC
300 mil
Pb-free
8-lead
SOIC
200 mil
Pb-free
Package
Comments
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2013
Revision: 1.4
1/42
ESMT
GENERAL DESCRIPTION
The F25L64QA is a 64Megabit, 3V only CMOS Serial Flash
memory device. The device supports the standard Serial
Peripheral Interface (SPI), and a Dual/Quad SPI. ESMT’s
memory devices reliably store memory data even after 100,000
programming and erase cycles.
The memory array can be organized into 32,768 programmable
pages of 256 byte each. 1 to 256 byte can be programmed at a
time with the Page Program instruction.
The device features sector erase architecture. The memory array
F25L64QA
is divided into 2,048 uniform sectors with 4K byte each; 256
uniform blocks with 32K byte each; 128 uniform blocks with 64K
byte each. Sectors can be erased individually without affecting
the data in other sectors. Blocks can be erased individually
without affecting the data in other blocks. Whole chip erase
capabilities provide the flexibility to revise the data in the device.
The device has Sector, Block or Chip Erase but no page erase.
The sector protect/unprotect feature disables both program and
erase operations in any combination of the sectors of the
memory.
FUNCTIONAL BLOCK DIAGRAM
Page Address
Latch / Counter
High Voltage
Generator
Memory
Array
Page Buffer
Status
Register
Byte Address
Latch / Counter
Y-Decoder
Command and Conrol Logic
Serial Interface
CE
SCK
SI
(SIO
0
)
SO
WP
HOLD
(SIO
1
) (SIO
2
) (SIO
3
)
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2013
Revision: 1.4
2/42
ESMT
PIN CONFIGURATIONS
8-Lead SOIC / 8-Lead VSOP
(SOIC 8L, 208mil Body, 1.27mm Pin Pitch)
(SOIC 8L, 208mil Body with thickness 1.0mm, 1.27mm Pin Pitch)
F25L64QA
CE
1
8
V
DD
SO / SIO
1
2
7
HOLD / SIO
3
WP / SIO
2
3
6
SCK
V
SS
4
5
SI / SIO
0
16-Lead SOIC
(SOIC 16L, 300mil Body, 1.27mm Pin Pitch)
HOLD / SIO
3
V
DD
1
2
16
15
SCK
SI / SIO
0
NC
NC
3
4
14
13
NC
NC
NC
NC
5
6
12
11
NC
NC
CE
SO / SIO
1
7
8
10
9
V
SS
WP / SIO
2
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2013
Revision: 1.4
3/42
ESMT
8-Contact WSON
(WSON 8C, 6mmX5mm Body, 1.27mm Contact Pitch)
F25L64QA
CE
1
8
V
DD
SO / SIO
1
2
7
HOLD / SIO
3
WP / SIO
2
3
6
SCK
V
SS
4
5
SI / SIO
0
PIN DESCRIPTION
Symbol
SCK
Pin Name
Serial Clock
Serial Data Input /
Serial Data Input Output 0
Functions
To provide the timing for serial input and output operations
To transfer commands, addresses or data serially into the device. Data is
latched on the rising edge of SCK (for Standard read mode). / Bidirectional IO
pin to transfer commands, addresses or data serially into the device on the
rising edge of SCK and read data or status from the device on the falling edge
of SCK(for Dual/Quad mode).
To transfer data serially out of the device. Data is shifted out on the falling edge
of SCK (for Standard read mode). / Bidirectional IO pin to transfer commands,
addresses or data serially into the device on the rising edge of SCK and read
data or status from the device on the falling edge of SCK (for Dual/Quad
mode).
To activate the device when CE is low.
The Write Protect (
WP
) pin is used to enable/disable BPL bit in the status
register. / Bidirectional IO pin to transfer commands, addresses or data serially
into the device on the rising edge of SCK and read data or status from the
device on the falling edge of SCK (for Quad mode).
To temporality stop serial communication with SPI flash memory without
resetting the device. / Bidirectional IO pin to transfer commands, addresses or
data serially into the device on the rising edge of SCK and read data or status
from the device on the falling edge of SCK (for Quad mode).
To provide power.
SI / SIO
0
SO / SIO
1
Serial Data Output /
Serial Data Input Output 1
Chip Enable
Write Protect /
Serial Data Input Output 2
CE
WP
/ SIO
2
HOLD / SIO
3
V
DD
V
SS
Hold /
Serial Data Input Output 3
Power Supply
Ground
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2013
Revision: 1.4
4/42
ESMT
SECTOR STRUCTURE
Table 1: Sector Address Table
64KB
Block
32KB
Block
255
127
254
Sector
2047
:
2040
2039
:
2032
2031
:
2024
2023
:
2016
2015
:
2008
2007
:
2000
Sector Size
(Kbytes)
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
Address range
7FF000h – 7FFFFFh
:
7F8000h – 7F8FFFh
7F7000h – 7F7FFFh
:
7F0000h – 7F0FFFh
7EF000h – 7EFFFFh
:
7E8000h – 7E8FFFh
7E7000h –7E7FFFh
:
7E0000h – 7E0FFFh
7DF000h – 7DFFFFh
:
7D8000h – 7D8FFFh
7D7000h – 7D7FFFh
:
7D0000h – 7D0FFFh
F25L64QA
individual
16 sectors
unit: 4KB
253
126
252
251
125
250
individual
block unit:
64KB
5
2
4
3
1
2
1
0
0
47
:
40
39
:
32
31
:
24
23
:
16
15
:
8
7
:
0
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
02F000h – 02FFFFh
:
028000h – 028FFFh
027000h – 027FFFh
:
020000h – 020FFFh
01F000h – 01FFFFh
:
018000h – 018FFFh
017000h – 017FFFh
:
010000h – 010FFFh
00F000h – 00FFFFh
:
008000h – 008FFFh
007000h – 007FFFh
:
000000h – 000FFFh
individual
16 sectors
unit: 4KB
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2013
Revision: 1.4
5/42
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
