UTRON
Rev. 1.3
UT62L64C
8K X 8 BIT LOW POWER CMOS SRAM
REVISION HISTORY
REVISION
Rev. 0.1
Rev. 1.0
Rev. 1.1
DESCRIPTION
Original
Release
Revised
-
Improve I
DR
from 20µA to 10µA (LL-version , max.)
1. Revised Single power supply : 3.3V 3.0V~3.6V
2. Add Extended temperature : -20
℃
~85
℃
3. Revised “Order information” : add Extended parts
4. AC/DC characteristics :
-add Extended temperature
-Icc1 (TYP):12 6mA, Icc1 (MAX) : 20 10mA
-Icc2 (TYP):6 12mA, Icc2(MAX) : 10 20mA
Add order information for lead free product
Released Date
May 3,2001
Feb.26,2002
May 14,2002
Rev. 1.2
Jul 30,2002
Rev. 1.3
May 15,2003
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80060
1
UTRON
Rev. 1.3
UT62L64C
8K X 8 BIT LOW POWER CMOS SRAM
GENERAL DESCRIPTION
FEATURES
Access time : 35/70ns (max.)
Low power consumption:
Operating : 30/20 mA (typical)
Standby : 1.5mA (typical) normal
1
µA
(typical) L-version
0.5
µA
(typical) LL-version
Single 3.0V~3.6V power supply
Operating temperature :
Commerical : 0
℃
~70
℃
Extended : -20
℃
~85
℃
All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Data retention voltage : 1.5V (min.)
Package : 28-pin 600mil PDIP
28-pin 330 mil SOP
Substrate connected : Vcc
The UT62L64C is a 65,536-bits low power
CMOS static random access memory organized
as 8,192 words by 8 bits. It is fabricated using
high performance, high reliability CMOS
technology.
Easy memory expansion is provided by using
two chip enable input.( CE ,CE2) The
UT62L64C operates from a single 3.3V power
supply and all inputs and outputs are fully TTL
compatible.
PIN CONFIGURATION
NC
A12
A7
A6
A5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
WE
CE2
A8
A9
A11
OE
UT62L64C
FUNCTIONAL BLOCK DIAGRAM
8K
×
8
MEMORY
ARRAY
A4
A3
A2
A10
CE
I/O8
I/O7
I/O6
I/O5
I/O4
A0-A12
DECODER
A1
A0
I/O1
Vcc
Vss
I/O2
I/O3
Vss
SOP/PDIP
I/O1-I/O8
I/O DATA
CIRCUIT
COLUMN I/O
PAD DESCRIPTION
SYMBOL
A0 - A12
I/O1 - I/O8
CE ,CE2
WE
OE
V
CC
V
SS
NC
CE
CE2
OE
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Enable Inputs
Write Enable Input
Output Enable Input
Power Supply
Ground
CONTROL
CIRCUIT
WE
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80060
2
UTRON
Rev. 1.3
UT62L64C
8K X 8 BIT LOW POWER CMOS SRAM
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Terminal Voltage with Respect to V
SS
Commerical
Operating Temperature
Extended
Storage Temperature
Power Dissipation
DC Output Current
Soldering Temperature (under 10 sec)
SYMBOL
V
TERM
T
A
T
A
T
STG
P
D
I
OUT
Tsolder
RATING
-0.5 to 4.5
0 to 70
-20 to 85
-65 to 150
1
50
260
UNIT
V
℃
℃
℃
W
mA
℃
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect
device reliability.
TRUTH TABLE
MODE
Standby
Standby
Output Disable
Read
Write
CE
H
X
L
L
L
CE2
X
L
H
H
H
OE
X
X
H
L
X
WE
X
X
H
H
L
I/O OPERATION
High - Z
High - Z
High - Z
D
OUT
D
IN
SUPPLY CURRENT
I
SB,
I
SB1
I
SB,
I
SB1
I
CC,
I
CC1,
I
CC2
I
CC,
I
CC1,
I
CC2
I
CC,
I
CC1,
I
CC2
note: H = V
IH
, L=V
IL
, X = Don't care.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 3.0~3.6V, T
A
= 0℃ to 70℃ / -20℃ to 85℃(E))
PARAMETER
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage
Current
Output High Voltage
Output Low Voltage
SYMBOL
＊
1
V
IH
V
IL
I
LI
＊
2
TEST CONDITION
MIN. TYP. MAX.
UNIT
2.2
-
VCC+0.5
V
- 0.5
-1
-1
2.4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
30
20
6
12
1
0.3
1.5
1
0.5
0.6
1
1
-
0.4
40
30
10
20
10
3
5
100
50
V
µA
µA
V
V
mA
mA
mA
mA
mA
mA
mA
µA
µA
V
SS
≦
V
IN
≦
V
CC
V
SS
≦
V
I/O
≦
V
CC
I
LO
V
OH
V
OL
I
CC
CE
= V
IH
or CE2= V
IL
or
OE
= V
IH
or
WE
= V
IL
I
OH
= - 1mA
I
OL
= 4mA
Cycle time=Min,I
I/O
= 0mA
CE
= V
IL
, CE2= V
IH
at 0.2V or Vcc-0.2V;
=1us
TCycle
=500ns
Normal
- L/- LL
Normal
-L
- LL
- 35
- 70
Operating Power
Supply Current
Icc1
Icc2
CE
=0.2V; I
I/O
= 0mA other pins TCycle
CE
=0.2V; I
I/O
= 0mA
other pins at 0.2V or Vcc-0.2V
Standby Current (TTL)
Standby current
(CMOS)
I
SB
CE
= V
IH
or CE2= V
IL
other pins=V
IL
or V
IH
CE
≧
V
CC
-0.2V
or CE2
≦
0.2V ,
other pins at 0.2V or Vcc-0.2V
I
SB
1
Notes:
1. Overshoot : Vcc+3.0v for pulse width less than 10ns.
2. Undershoot : Vss-3.0v for pulse width less than 10ns.
3. Overshoot and Undershoot are sampled, not 100% tested.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80060
3
UTRON
Rev. 1.3
UT62L64C
8K X 8 BIT LOW POWER CMOS SRAM
CAPACITANCE
(T
A
=25
℃
, f=1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
C
IN
C
I/O
MIN.
-
-
MAX
8
10
UNIT
pF
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0V to 3.0V
5ns
1.5V
C
L
= 100pF, I
OH
/I
OL
= -1mA/4 mA
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 3.0~3.6V, T
A
= 0
℃
to 70
℃
/ -20
℃
to 85
℃
(E))
(1) READ CYCLE
PARAMETER
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low-Z
Output Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
(2) WRITE CYCLE
PARAMETER
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write-Time
Output Active from End of Write
Write to Output in High-Z
SYMBOL
UT62L64C-35
MIN.
MAX.
SYMBOL
UT62L64C-35
MIN.
MAX.
UT62L64C-70
MIN.
MAX.
UNIT
t
RC
t
AA
t
ACE
t
OE
t
CLZ*
t
OLZ*
t
CHZ*
t
OHZ*
t
OH
35
-
-
-
10
5
-
-
5
-
35
35
25
-
-
25
25
-
70
-
-
-
10
5
-
-
5
-
70
70
35
-
-
35
35
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
UT62L64C-70
MIN.
MAX.
UNIT
t
WC
t
AW
t
CW
t
AS
t
WP
t
WR
t
DW
t
DH
t
OW*
t
WHZ*
35
30
30
0
25
0
20
0
5
-
-
-
-
-
-
-
-
-
-
15
70
60
60
0
50
0
30
0
5
-
-
-
-
-
-
-
-
-
-
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*These parameters are guaranteed by device characterization, but not production tested.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80060
4
UTRON
Rev. 1.3
UT62L64C
8K X 8 BIT LOW POWER CMOS SRAM
TIMING WAVEFORMS
READ CYCLE 1
(Address Controlled)
(1,2)
t
RC
Address
t
AA
t
OH
Dout
Previous data valid
Data Valid
t
OH
READ CYCLE 2
(
CE
and
CE2
and
OE
Controlled)
(1,3,4,5)
t
RC
Address
t
AA
CE
t
ACE
CE2
OE
t
OE
t
CLZ
t
OLZ
Dout
High-Z
Data Valid
t
CHZ
t
OHZ
t
OH
High-Z
Notes :
1.
WE
is high for read cycle.
2.Device is continuously selected OE =low, CE =low
,
CE2=high
.
3.Address must be valid prior to or coincident with CE =low
,
CE2=high; otherwise t
AA
is the limiting parameter.
4.t
CLZ
, t
OLZ
, t
CHZ
and t
OHZ
are specified with C
L
=5pF. Transition is measured± 500mV from steady state.
5.At any given temperature and voltage condition, t
CHZ
is less than t
CLZ,,
t
OHZ
is less than t
OLZ
.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80060
5
51单片机
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