CH7006C
Chrontel
CHRONTEL
CHRONTEL
Digital PC to TV Encoder Features
1. F
EATURES
• Function compatible with CH7004
• Universal digital interface accepts YCrCb (CCIR601
or 656) or RGB (15, 16 or 24-bit) video data in both
non-interlaced and interlaced formats
• True scale rendering engine supports underscan
operations for various graphic resolutions
† ¥
• Enhanced text sharpness and adaptive flicker removal
with up to 5-lines of filtering
†
• Enhanced dot crawl control and area reduction
• Fully programmable through serial port
• Supports NTSC, NTSC-EIA (Japan), and PAL (B, D,
G, H, I, M and N) TV formats
• Provides Composite, S-Video and SCART outputs
• Auto-detection of TV presence
• Supports VBI pass-through
• Programmable power management
• 9-bit video DAC outputs
• Complete Windows and DOS driver software
• Offered in 44-pin LQFP
2. G
ENERAL
D
ESCRIPTION
Chrontel’s CH7006 digital PC to TV encoder is a stand-
alone integrated circuit which provides a PC 99 compliant
solution for TV output. It provides a universal digital
input port to accept a pixel data stream from a compatible
VGA controller (or equivalent) and converts this directly
into NTSC or PAL TV format.
This circuit integrates a digital NTSC/PAL encoder with
9-bit DAC interface, and new adaptive flicker filter, and
high accuracy low-jitter phase locked loop to create
outstanding quality video. Through its true scale scaling
and deflickering engine, the CH7006 supports full vertical
and horizontal underscan capability and operates in 5
different resolutions including 640x480 and 800x600.
A new universal digital interface along with full
programmability make the CH7006 ideal for system-level
PC solutions. All features are software programmable
through a standard serial port, to enable a complete PC
solution using a TV as the primary display.
†
Patent number 5,781,241
¥
Patent number 5,914,753
LINE
MEMORY
YUV-RGB CONVERTER
RGB-YUV
CONVERTER
DIGITAL
D[15:0]
PIXEL DATA
INPUT
INTERFACE
TRUE SCALE
SCALING &
DEFLICKERING
ENGINE
NTSC/PAL
ENCODER
& FILTERS
Y/R
TRIPLE
DAC
C/G
CVBS/B
SYSTEM CLOCK
RSET
SERIAL PORT
CONTROLLER
PLL
TIMING & SYNC
GENERATOR
SC
SD
RESET*
XCLK
H
V
XI
XO/FIN CSYNC P-OUT DS/BCO
Figure 1: Functional Block Diagram
201-0000-026
Rev. 2.8, 6/24/2004
1
CHRONTEL
3. P
IN
D
ESCRIPTIONS
3.1 Package Diagram
CH7006C
DS/BCO
35
P-OUT
DGND
D[2]
44
43
42
41
40
39
XCLK
D[1]
D[0]
38
37
36
D[3]
D[4]
D[5]
D[6]
DVDD
D[7]
D[8]
DGND
D[9]
D[10]
D[11]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
34
33
32
31
AGND
DVDD
V
CHRONTEL
CH7006
H
XO/FIN
XI
AVDD
DVDD
RESET*
ADDR
DGND
SC
SD
VDD
RSET
GND
30
29
28
27
26
25
24
23
D[12]
D[13]
D[14]
D[15]
C/G
CSYNC
DGND
DVDD
GND
Figure 2: 44-Pin LQFP
2
CVBS/B
Y/R
201-0000-026
Rev. 2.8, 6/24/2004
CHRONTEL
3.2 Pin Descriptions
Table 1. Pin Descriptions
44Pin
LQFP
1,2,
3,4,
6,7,9,
10,11,
12,13,
14,15,
42,43,
44
37
CH7006C
Type
In
Symbol
D15-D0
Description
Digital Pixel Inputs
These pins accept digital pixel data streams with either 8, 12, or 16-bit multiplexed or
16-bit non-multiplexed formats, determined by the input mode setting (see
Registers
and Programming
section). Inputs D0 - D7 are used when operating in 8-bit
multiplexed mode. Inputs D0 - D11 are used when operating in 12-bit mode. Inputs
D0 - D15 are used when operating in 16-bit mode. The data structure and timing
sequence for each mode is described in the section on Digital Input Port.
Pixel Clock Output
The CH7006, operating in master mode, provides a pixel data clocking signal to the
VGA controller. This clock will only be provided in master clock modes and will be tri-
stated otherwise. This pin provides the pixel clock output signal (adjustable as 1X,2X
or 3x) to the VGA controller (see the section on Digital Video Interface, Registers and
Programming for more details). The capacitive loading on this pin should be kept to a
minimum.
Pixel Clock Input
To operate in a pure master mode, the P-OUT signal should be connected to the
XCLK input pin. To operate in a pseudo-master mode, the P-OUT clock is used as a
reference frequency, and a signal locked to this output (at 1X, 1/2X, or 1/3X the P-
OUT frequency) is input to the XCLK pin. To operate in slave mode, the CH7006
accepts an external pixel clock input at this pin. The capacitive loading on this pin
should be kept to a minimum.
Vertical Sync Input/Output
This pin accepts the vertical sync signal from the VGA controller, or outputs a vertical
sync to the VGA controller. The capacitive loading on this pin should kept to a
minimum.
Horizontal Sync Input/Output
This pin accepts the horizontal sync from the VGA controller, or outputs a horizontal
sync to the VGA controller. The capacitive loading on this pin should be kept to a
minimum.
Data/Start (input) / Buffered Clock (output)
When configured as an input, the rising edge of this signal identifies the first active
pixel of data for each active line.
When configured as an output this pin provides a buffered clock output. The output
clock can be selected using the BCO register (17h) (see Registers and
Programming).
Out
P-OUT
39
In
XCLK
41
In/Out
V
40
In/Out
H
35
In/Out
DS/BCO
32
In
XI
Crystal Input
A parallel resonance 14.31818 MHz (± 50 ppm) crystal should be attached between
XI and XO/FIN. However, if an external CMOS clock is attached to XO/FIN, XI should
be connected to ground.
Crystal Output or External Fref
A 14.31818 MHz (± 50 ppm) crystal may be attached between XO/FIN and XI. An
external CMOS compatible clock can be connected to XO/FIN as an alternative.
Reference Resistor
A 360
Ω
resistor with short and wide traces should be attached between RSET and
ground. No other connections should be made to this pin.
Luminance Output
A 75
Ω
termination resistor with short traces should be attached between Y and
ground for optimum performance. In normal operating modes other than SCART and
RGB bypass, this pin outputs the composite video signal. In SCART and RGB
Bypass modes, this pin outputs the red signal.
33
In
XO/FIN
24
In
RSET
22
Out
Y/R
201-0000-026
Rev. 2.8, 6/24/2004
3
CHRONTEL
Table 1. Pin Descriptions
44Pin
LQFP
21
CH7006C
Symbol
C/G
Type
Out
Description
Chrominance Output
A 75
Ω
termination resistor with short traces should be attached between C and
ground for optimum performance. In normal operating modes other than SCART and
RGB bypass, this pin outputs the composite video signal. In SCART and RGB
Bypass modes, this pin outputs the green signal.
Composite Video Output
A 75
Ω
termination resistor with short traces should be attached between CVBS and
ground for optimum performance. In normal operating modes other than SCART and
RGB bypass, this pin outputs the composite video signal. In SCART and RGB
Bypass modes, this pin outputs the blue signal.
Composite Sync Output
A 75
Ω
termination resistor with short traces should be attached between CSYNC
and ground for optimum performance. In SCART mode, this pin outputs the
composite sync signal.
Serial Data (External pull-up required)
This pin functions as the serial data pin of the serial port, and uses the DVDD supply
and is not 5V tolerant.
Serial Clock (Internal pull-up)
This pin functions as the serial clock pin of the serial port, and uses the DVDD supply
and is not 5V tolerant.
Reset Input
When this pin is low, the CH7006 is held in the power-on reset condition. When this
pin is high, the device operates normally and reset is controlled through the serial
port register.
Analog ground
This pin provides the ground reference for the analog section of the CH7006, and
MUST be connected to the system ground, to prevent latchup. Refer to the
Application Information
section for information on proper supply decoupling.
Analog Supply Voltage
This pins supplies the 5V power to the analog section of the CH7006.
DAC Power Supply
This pins supplies the 5V power to CH7006’s internal DAC’s.
DAC Ground
These pins provide the ground reference for CH7006’s internal DACs. For
information on proper supply decoupling, please refer to the Application Information
section.
Digital Supply Voltage
These pins supply the 3.3V power to the digital section of CH7006.
Digital Ground
These pins provide the ground reference for the digital section of CH7006, and
MUST be connected to the system ground to prevent latchup.
20
Out
CVBS/B
17
Out
CSYNC
26
In/Out
SD
27
In
SC
29
In
Reset*
34
Power
AGND
31
25
19,23
Power
Power
Power
AVDD
VDD
GND
5,16,
30,38
8,18,
28,36
Power
Power
DVDD
DGND
4
201-0000-026
Rev. 2.8, 6/24/2004
CHRONTEL
4. D
IGITAL
V
IDEO
I
NTERFACE
CH7006C
The CH7006 digital video interface provides a flexible digital interface between a computer graphics controller and
the TV encoder IC, forming the ideal quality/cost configuration for performing the TV-output function. This digital
interface consists of up to 16 data signals and 4 control signals, all of which are subject to programmable control
through the CH7006 register set. This interface can be configured as 8, 12 or 16-bit inputs operating in either
multiplexed mode or 16-bit input operation in demultiplexed mode. It will also accept either YCrCb or RGB (15, 16
or 24-bit) data formats and will accept both non-interlaced and interlaced data formats. A summary of the data
format modes is as follows:
Table 2. Input Data Formats
Bus
Width
Transfer Mode
Color Space and Depth
Format Reference
16-bit
15-bit
16-bit
8-bit
8-bit
8-bit
8-bit
12-bit
12-bit
16-bit
Non-multiplexed
Non-multiplexed
Non-multiplexed
2X-multiplexed
2X-multiplexed
3X-multiplexed
2X-multiplexed
2X-multiplexed
2X-multiplexed
2X-multiplexed
RGB 16-bit
RGB 15-bit
YCrCb (24-bit)
RGB 15-bit
RGB 16-bit
RGB 24-bit
YCrCb (24-bit)
RGB 24
RGB 24
RGB 24 (32)
5-6-5 each word
5-5-5 each word
CbY0,CrY1...(CCIR656 style)
5-5-5 over two bytes
5-6-5 over two bytes
8-8-8 over three bytes
Cb,Y0,Cr,Y1,(CCIR656 style)
8-8-8 over two words - ‘C’ version
8-8-8 over two words - ‘I’ version
8-8,8X over two words
The clock and timing signals used to latch and process the incoming pixel data is dependent upon the clock mode.
The CH7006 can operate in either master (the CH7004 generates a pixel frequency which is either returned as a
phase-aligned pixel clock or used directly to latch data), or slave mode (the graphics chip generates the pixel clock).
The pixel clock frequency will change depending upon the active image size (e.g., 640x480 or 800x600), the desired
output format (NTSC or PAL), and the amount of scaling desired. The pixel clock may be requested to be 1X, 2X,
or 3X the pixel data rate (subject to a 100MHz frequency limitation). In the case of a 1X pixel clock the CH7006
will automatically use both clock edges, if a multiplexed data format is selected.
Sync Signals:
Horizontal and vertical sync signals will normally be supplied by the VGA controller, but may be
selected to be generated by the CH7006. In the case of CCIR656 style input (IDF = 1 or 9), embedded sync may
also be used. (In each case, the period of the horizontal sync should be equal to the duration of the pixel clock, time
the first value of the (Total
Pixels/line
x
Total Lines/Frame)
column of
Table 17
on page 24 (Display Mode Register
00H description). The leading edge of the horizontal sync is used to determine the start of each line. The Vertical
sync signal must be able to be set to the second value in the (Total
Pixels/Line
x
Total Lines/Frame)
column of
Table 17
on page 24.)
Master Clock Mode:
The CH7006 generates a clock signal (output at the P-OUT pin) which will be used by the
VGA controller as a frequency reference. The VGA controller will then generate a clock signal which will be input
via the XCLK input. This incoming signal will be used to latch (and de-multiplex, if required) incoming data. The
XCLK input clock rate must match the input data rate, and the P-OUT clock can be requested to be 1X, 2X or 3X
the pixel data rate. As an alternative, the P-OUT clock signal can also be used as the input clock signal (connected
directly to the XCLK input) to latch the incoming data. If this mode is used, the incoming data must meet setup and
hold times with respect to the XCLK input (with the only internal adjustment being XCLK polarity).
Slave Clock Mode:
The VGA controller will generate a clock which will be input to the XCLK pin (no clock
signal will be output on the P-OUT pin). This signal must match the input data rate, must occur at 1X, 2X or 3X the
pixel data rate, and will be used to latch (and de-multiplex if required) incoming data. Also, the graphics IC
transmits back to the TV encoder the horizontal and vertical timing signals, and pixel data, each of which must meet
the specified setup and hold times with respect to the pixel clock.
Pixel Data:
Active pixel data will be expected after a programmable number pixels times the multiplex rate after
the leading edge of Horizontal Sync. In other words, specifying the horizontal back porch value (as a pixel count),
plus horizontal sync width, will determine when the chip will begin to sample pixels.
201-0000-026
Rev. 2.8, 6/24/2004
5
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