CH7003B
CHRONTEL
Digital PC to TV Encoder
Features
• Input data path handles 8, 12, or 16-bit words in
multiplexed or non-multiplexed form
• Decodes pixel data in YCrCb (CCIR601 or 656) or
RGB (15, 16 or 24-bit) formats
• Supports 640x480, 640x400, 720x400, 800x600 and
512x384 input resolutions
• Adjustable underscan for most modes
† ¥
• High quality 4-line flicker filtering
†
• High resolution on-chip PLL
• Fully programmable through I
2
C port
• Supports NTSC, NTSC-EIA (Japan), and PAL (B, D,
G, H, I, M and N) TV formats
• Provides Composite, S-Video and SCART outputs
• CCIR624-3 compliant (see exceptions)
• Auto-detection of TV presence
• Sub-carrier genlock and dot crawl control
• Programmable power management
• 9-bit video DAC outputs
• Complete Windows and DOS driver software
• Offered in a 44-pin PLCC, 44-pin TQFP
General Description
Chrontel’s CH7003 digital PC to TV encoder is a stand-
alone integrated circuit which provides a PC 99 compliant
solution for TV output. It provides a universal digital input
port to accept a pixel data stream from a compatible VGA
controller (or equivalent) and converts this directly into
NTSC or PAL TV format, with simultaneous composite
and S-Video outputs.
This circuit integrates a digital NTSC/PAL encoder with 9-
bit DAC interface, and new adaptive flicker filter, and high
accuracy low-jitter phase locked loop to create outstanding
quality video. Through its TrueScale
TM
scaling and de-
flickering engine, the CH7003 supports full vertical and
horizontal underscan capability and operates in 5 different
resolutions including 640x480 and 800x600.
A new universal digital interface along with full
programmability make the CH7003 ideal for system-level
PC solutions. All features are software programmable
through a standard I
2
C port, to enable a complete PC
solution using a TV as the primary display.
†
Patent number 5,781,241
¥
Patent number 5,914,753
LINE
MEMORY
YUV-RGB CONVERTER
RGB-YUV
CONVERTER
DIGITAL
D[15:0 ]
PIXEL DATA
INPUT
INTERFACE
TRUE SCALE
SCALING & DEFLICKERING
ENGINE
NTSC/PAL
ENCODER
& FILTERS
Y/R
TRIPLE
DAC
C/G
CVBS/G
SYSTEM CLOCK
RSET
I
2
C REGISTER & CONTROL
BLOCK
PLL
TIMING & SYNC GENERATOR
SC
SD
ADDR
XCLK
H
V
XI XO/FIN CSYNC P-OUT BCO
Figure 1: Functional Block Diagram
201-0000-023 Rev 4.1, 8/2/99
1
CHRONTEL
CH7003B
P-OUT
DGND
6
5
4
3
2
1
44
43
42
41
D[3]
D[4]
D[5]
D[6]
DVDD
D[7]
D[8]
DGND]
D[9]
D[10]
D[11]
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
40
39
38
37
36
AGND
DVDD
XCLK
BCO
D[2]
D[1]
D[0]
H
V
XO/FIN
XI
AVDD
DVDD
ADDR
DGND
SC
SD
VDD
RSET
GND
CHRONTEL
CH7003
35
34
33
32
31
30
29
DVDD
CSYNC
DGND
GND
CVBS
C
D[12]
D[13]
D[14]
Figure 2: 44-pin PLCC
2
D[15]
Y
201-0000-023 Rev.4.1, 8/2/99
CHRONTEL
Figure 3: 44-pin TQFP
CH7003B
P-OUT
DGND
44
43
42
41
40
39
38
37
36
35
D[3]
D[4]
D[5]
D[6]
DVDD
D[7]
D[8]
DGND]
D[9]
D[10]
D[11]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
34
33
32
31
30
AGND
DVDD
XCLK
BCO
D[2]
D[1]
D[0]
H
V
XO/FIN
XI
AVDD
DVDD
ADDR
DGND
SC
SD
VDD
RSET
GND
CHRONTEL
CH7003
29
28
27
26
25
24
23
DVDD
CSYNC
DGND
GND
CVBS
C
D[12]
D[13]
D[14]
Figure 3: 44-PIN TQFP
201-0000-023 Rev 4.1, 8/2/99
D[15]
Y
3
CHRONTEL
Table 1. Pin Description
44-Pin
PLLC
21-15,
13-12,
10-4
CH7003B
Type
In
44-Pin
TQFP
15,14,
13,12,
11,10,
9,7,6,4,
3,2,
1,44,43,
42
37
Symbol
D15-D0
Description
Digital Pixel Inputs
These pins accept digital pixel data streams with either 8, 12, or 16-bit
multiplexed or 16-bit non-multiplexed formats, determined by the input
mode setting (see
Registers and Programming
section). Inputs D0 - D7 are
used when operating in 8-bit multiplexed mode. Inputs D0 - D11 are used
when operating in 12-bit mode. Inputs D0 - D15 are used when operating
in 16-bit mode. The data structure and timing sequence for each mode is
described in the section on
Digital Video Interface.
Pixel Clock Output
The CH7003, operating in master mode, provides a pixel data clocking
signal to the VGA controller. This pin provides the pixel clock output signal
(adjustable as 1X, 2X or 3X) to the VGA controller (see the section on
Digital Video Interface
and
Registers and Programming
for more details).
The capacitive loading on this pin should be kept to a minimum.
Pixel Clock Input
To operate in a pure master mode, the P-OUT signal should be connected
to the XCLK input pin. To operate in a pseudo-master mode, the P-OUT
clock is used as a reference frequency, and a signal locked to this output (at
1X, 1/2X, or 1/3X the P-OUT frequency) is input to the XCLK pin. To operate
in slave mode, the CH7003 accepts an external pixel clock input at this pin.
The capacitive loading on this pin should be kept to a minimum.
Vertical Sync Input/Output
This pin accepts the vertical sync signal from the VGA controller, or outputs
a vertical sync to the VGA controller. The capacitive loading on this pin
should kept to a minimum.
Horizontal Sync Input/Output
This pin accepts the horizontal sync from the VGA controller, or outputs a
horizontal sync to the VGA controller. The capacitive loading on this pin
should be kept to a minimum.
Buffered Clock Output
This pin provides a buffered output of the 14.31818 MHz crystal input
frequency for other devices and remains active at all times (including
power-down). The output can also be selected to be other frequencies (see
Registers and Programming).
Crystal Input
A parallel resonance 14.31818 MHz (± 50 ppm) crystal should be attached
between XI and XO/FIN. However, if an external CMOS clock is attached to
XO/FIN, XI should be connected to ground.
Crystal Output or External Fref
A 14.31818 MHz (± 50 ppm) crystal may be attached between XO/FIN and
XI. An external CMOS compatible clock can be connected to XO/FIN as an
alternative.
Reference Resistor
A 360
Ω
resistor with short and wide traces should be attached between
RSET and ground. No other connections should be made to this pin.
Luminance Output
A 75
Ω
termination resistor with short traces should be attached between Y
and ground for optimum performance.
In normal operating modes other
than SCART, this pin outputs the luma video signal. In SCART mode, this
pin outputs the red signal.
Chrominance Output
A 75
Ω
termination resistor with short traces should be attached between C
and ground for optimum performance.
In normal operating modes other
than SCART, this pin outputs the chroma video signal. In SCART mode,
this pin outputs the green signal.
43
Out
P-OUT
1
39
In
XCLK
3
41
In/Out
V
2
40
In/Out
H
41
35
Out
BCO
38
32
In
XI
39
33
In
XO/FIN
30
24
In
RSET
28
22
Out
Y/R
27
21
Out
C/G
4
201-0000-023 Rev.4.1, 8/2/99
CHRONTEL
Table 1. Pin Description
(continued)
44-Pin
PLLC
26
CH7003B
Type
Out
44-Pin
TQFP
20
Symbol
CVBS/B
Description
Composite Video Output
A 75
Ω
termination resistor with short traces should be attached between
CVBS and ground for optimum performance. In normal operating modes
other than SCART, this pin outputs the composite video signal. In SCART
mode, this pin outputs the blue signal.
Composite Sync Output
A 75
Ω
termination resistor with short traces should be attached between
CSYNC and ground for optimum performance. In SCART mode, this pin
outputs the composite sync signal.
Serial Data (External pull-up required)
This pin functins as SD, the serial data pin of the I
2
C interface port (see the
I
2
C Port Operation
section for details).
Serial Clock (Internal pull-up)
This pin functions as the serial clock pin of the I
2
C interface port (see the
I
2
C Port Operation
section for details).
I
2
C Address Select (Internal pull-up)
This pin is the I
2
C Address Select, which corresponds to bits 1 and 0 of the
I
2
C device address (see the
I
2
C Port Operation
section for details), creating
an address selection as follows:
ADDR
I2C Address Selected
1
1110101 = 75H = 117
0
1110110 = 76H = 118
Analog ground
These pins provide the ground reference for the analog section of CH7003,
and MUST be connected to the system ground, to prevent latchup.
Analog Supply Voltage
These pins supply the 5V power to the analog section of the CH7003.
DAC Power Supply
These pins supply the 5V power to CH7003’s internal DACs.
DAC Ground
These pins provide the ground reference for CH7003’s internal DACs.
Digital Supply Voltage
These pins supply the 3.3V power to the digital section of CH7003.
Digital Ground
These pins provide the ground reference for the digital section of CH7003,
and MUST be connected to the system ground to prevent latchup.
R (Red) Component Output
This pin provides the analog Red component of the digital RGB input in the
RGB Pass-Through mode.
G (Green) Component Output
This pin provides the analog Green component of the digital RGB input in
the RGB Pass-Through mode.
B (Blue) Component Output
This pin provides the analog Blue component of the digital RGB input in the
RGB Pass-Though mode.
23
17
Out
CSYNC
32
26
In/Out
SD
33
27
In
SC
35
29
In
ADDR
40
34
Power
AGND
37
31
29, 25
44, 36,
22, 11
42, 34,
24, 14
N/A
31
25
19,23
5,16,
30,38
8, 18,
28, 36
N/A
Power
Power
Power
Power
Power
AVDD
VDD
GND
DVDD
DGND
Out
R
N/A
N/A
Out
G
N/A
N/A
Out
B
201-0000-023 Rev 4.1, 8/2/99
5
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