ESMT
Flash
F25L16PA (2S)
16 Mbit Serial Flash Memory
with Dual
FEATURES
Single supply voltage 2.7~3.6V
Standard and Dual
Speed
- Read max frequency: 50MHz
- Fast Read max frequency: 50MHz / 86MHz / 100MHz
- Fast Read Dual max frequency: 50MHz / 86MHz / 100MHz
(100MHz / 172MHz / 200MHz equivalent Dual SPI)
Low power consumption
- Active current: 23.5 mA (max.)
- Standby current: 25
μ
A (max.)
- Deep Power Down current: 10
μ
A (max.)
Reliability
- 100,000 typical program/erase cycles
- 20 years Data Retention
Program
- Page programming time: 1.5 ms (typical)
Erase
- Chip Erase time 10 sec (typical)
- 64K bytes Block Erase time 1 sec (typical)
- 32K bytes Block Erase time 500 ms (typical)
- 4K bytes Sector Erase time 120 ms (typical)
Page Programming
- 256 byte per programmable page
Lockable 512 bytes OTP security sector
SPI Serial Interface
- SPI Compatible: Mode 0 and Mode 3
End of program or erase detection
Write Protect (
WP
)
Hold Pin ( HOLD )
All Pb-free products are RoHS-Compliant
ORDERING INFORMATION
Product ID
F25L16PA –50PG2S
F25L16PA –86PG2S
F25L16PA –100PG2S
F25L16PA –50PAG2S
F25L16PA –86PAG2S
F25L16PA –100PAG2S
F25L16PA –50PHG2S
F25L16PA –86PHG2S
F25L16PA –100PHG2S
F25L16PA –50DG2S
F25L16PA –86DG2S
F25L16PA –100DG2S
F25L16PA –50HG2S
F25L16PA –86HG2S
F25L16PA –100HG2S
Speed
50MHz
86MHz
100MHz
50MHz
86MHz
100MHz
50MHz
86MHz
100MHz
50MHz
86MHz
100MHz
50MHz
86MHz
100MHz
8-contact
WSON
6x5 mm
Pb-free
8-pin
PDIP
300 mil
Pb-free
16-lead
SOIC
300 mil
Pb-free
8-lead
SOIC
200 mil
Pb-free
8-lead
SOIC
150 mil
Pb-free
Package
Comments
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2012
Revision: 1.4
1/42
ESMT
GENERAL DESCRIPTION
The F25L16PA is a 16Megabit, 3V only CMOS Serial Flash
memory device. The device supports the standard Serial
Peripheral Interface (SPI), and a Dual SPI. ESMT’s memory
devices reliably store memory data even after 100,000
programming and erase cycles.
The memory array can be organized into 8,192 programmable
pages of 256 byte each. 1 to 256 byte can be programmed at a
time with the Page Program instruction.
The device features sector erase architecture. The memory array
F25L16PA (2S)
is divided into 512 uniform sectors with 4K byte each; 64 uniform
blocks with 32K byte each; 32 uniform blocks with 64K byte each.
Sectors can be erased individually without affecting the data in
other sectors. Blocks can be erased individually without affecting
the data in other blocks. Whole chip erase capabilities provide
the flexibility to revise the data in the device. The device has
Sector, Block or Chip Erase but no page erase.
The sector protect/unprotect feature disables both program and
erase operations in any combination of the sectors of the
memory.
FUNCTIONAL BLOCK DIAGRAM
Page Address
Latch / Counter
High Voltage
Generator
Memory
Array
Page Buffer
Status
Register
Byte Address
Latch / Counter
Y-Decoder
Command and Conrol Logic
Serial Interface
CE
SCK
SI
(SIO
0
)
SO
(SIO
1
)
WP
HOLD
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2012
Revision: 1.4
2/42
ESMT
PIN CONFIGURATIONS
8-Lead SOIC
(SOIC 8L, 150mil Body, 1.27mm Pin Pitch)
(SOIC 8L, 208mil Body, 1.27mm Pin Pitch)
F25L16PA (2S)
CE
1
8
V
DD
SO / SIO
1
2
7
HOLD
WP
3
6
SCK
V
SS
4
5
SI / SIO
0
16-Lead SOIC
(SOIC 16L, 300mil Body, 1.27mm Pin Pitch)
HOLD
V
DD
1
2
16
15
SCK
SI / SIO
0
NC
NC
3
4
14
13
NC
NC
NC
NC
5
6
12
11
NC
NC
CE
SO / SIO
1
7
8
10
9
V
SS
WP
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2012
Revision: 1.4
3/42
ESMT
8-Pin PDIP
(PDIP 8P, 300mil Body, 2.54mm Pin Pitch)
F25L16PA (2S)
CE
1
8
V
DD
SO / SIO
1
2
7
HOLD
WP
3
6
SCK
V
SS
4
5
SI / SIO
0
8- Contact WSON
(WSON 8C, 6mmX5mm Body, 1.27mm Contact Pitch)
CE
1
8
VDD
SO
2
7
HOLD
WP
3
6
SCK
VSS
4
5
SI
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2012
Revision: 1.4
4/42
ESMT
PIN DESCRIPTION
Symbol
SCK
Pin Name
Serial Clock
Serial Data Input /
Serial Data Input Output 0
Functions
F25L16PA (2S)
To provide the timing for serial input and output operations
To transfer commands, addresses or data serially into the device. Data is
latched on the rising edge of SCK (for Standard read mode). / Bidirectional IO
pin to transfer commands, addresses or data serially into the device on the
rising edge of SCK and read data or status from the device on the falling edge
of SCK(for Dual mode).
To transfer data serially out of the device. Data is shifted out on the falling edge
of SCK (for Standard read mode). / Bidirectional IO pin to transfer commands,
addresses or data serially into the device on the rising edge of SCK and read
data or status from the device on the falling edge of SCK (for Dual mode).
To activate the device when CE is low.
The Write Protect (
WP
) pin is used to enable/disable BPL bit in the status
register.
To temporality stop serial communication with SPI flash memory without
resetting the device.
To provide power.
SI / SIO
0
SO / SIO
1
Serial Data Output /
Serial Data Input Output 1
Chip Enable
Write Protect
Hold
Power Supply
Ground
CE
WP
HOLD
V
DD
V
SS
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2012
Revision: 1.4
5/42
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