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IDT71V3548S100BGI

器件型号:IDT71V3548S100BGI
文件大小:5147.09KB,共10页
厂商名称:IDT
厂商官网:http://www.idt.com/
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器件描述

256k x 18 3.3V synchronous zbt sram 3.3V I/O, burst counter pipelined outputs

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256K x 18
3.3V Synchronous ZBT SRAM
3.3V I/O, Burst Counter
Pipelined Outputs
x
x
IDT71V3548S
IDT71V3548SA
Features
256K x 18 memory configurations
Supports high performance system speed - 133 MHz
(4.2 ns Clock-to-Data Access)
ZBT
TM
Feature - No dead cycles between write and read
cycles
Internally synchronized output buffer enable eliminates the
need to control
OE
Single R/W (READ/WRITE) control pin
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
Individual byte write (BW
1
-
BW
4
) control (May tie active)
Three chip enables for simple depth expansion
3.3V power supply (±5%), 3.3V I/O Supply (V
DDQ)
Optional Boundary Scan JTAG Interface (IEEE 1149.1
compliant)
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA)
x
x
x
x
x
x
x
x
x
x
Description
The IDT71V3548 are 3.3V high-speed 4,718,592-bit (4.5 Megabit)
synchronous SRAMS. They are designed to eliminate dead bus
cycles when turning the bus around between reads and writes, or
writes and reads. Thus, they have been given the name ZBT
TM
, or
Zero Bus Turnaround.
Address and control signals are applied to the SRAM during one
clock cycle, and two cycles later the associated data cycle occurs, be it
read or write.
The IDT71V3548 contain data I/O, address and control signal
registers. Output enable is the only asynchronous signal and can be used
to disable the outputs at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V3548
to be suspended as long as necessary. All synchronous inputs are
ignored when (CEN) is high and the internal device registers will hold
their previous values.
There are three chip enable pins (CE
1
, CE
2
,
CE
2
) that allow the user
to deselect the device when desired. If any one of these three are not
asserted when ADV/LD is low, no new memory operation can be
initiated. However, any pending data transfers (reads or writes) will be
completed. The data bus will tri-state two cycles after chip is deselected
or a write is initiated.
The IDT71V3548 has an on-chip burst counter. In the burst
mode, the IDT71V3548 can provide four cycles of data for a single address
presented to the SRAM. The order of the burst sequence is defined by the
LBO
input pin. The
LBO
pin selects between linear and interleaved burst
sequence. The ADV/LD signal is used to load a new external address
(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =
HIGH).
The IDT71V3548 SRAMs utilize IDT's latest high-performance CMOS
process and are packaged in a JEDEC standard 14mm x 20mm 100- pin
plastic thin quad flatpack (TQFP) as well as a 119 ball grid array (BGA)
and 165 fine pitch ball grid array (fBGA).
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Static
Synchronous
Synchronous
N/A
Synchronous
Asynchronous
Synchronous
Synchronous
Static
Static
5296 tbl 01
Pin Description Summary
A
0
-A
17
CE
1
, CE
2
,
CE
2
OE
R/W
CEN
BW
1
,
BW
2
,
BW
3
,
BW
4
CLK
ADV/LD
LBO
TMS
TDI
TCK
TDO
TRST
ZZ
I/O
0
-I/O
15
, I/O
P1
-I/O
P2
V
DD
, V
DDQ
V
SS
Address Inputs
Chip Enables
Output Enable
Read/Write Signal
Clock Enable
Individual Byte Write Selects
Clock
Advance burst addre ss / Load new address
Linear / Interleaved Burst Order
Test Mode Select
Test Data Input
Test Clock
Test Data Output
JTAG Reset (Optional)
Sleep Mode
Data Input / Output
Core Power, I/O Power
Ground
MAY 2002
1
©2002 Integrated Device Technology, Inc.
DSC-5296/03
IDT71V3548, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Pin Definition
(1)
Symbol
A
0
-A
17
ADV/LD
Pin Function
Address Inputs
Advance / Load
I/O
I
I
Active
N/A
N/A
Description
Synchronous Address inputs. The address register is triggered by a combination of the rising
edge of CLK, ADV/LD low,
CEN
low, and true chip enables.
ADV/LD is a synchronous input that is used to load the internal registers with new address and
control when it is sampled low at the rising edge of clock with the chip selected. When
ADV/LD is low with the chip deselected, any burst in progress is terminated. When ADV/LD is
sampled high then the internal burst counter is advanced for any burst that was in progress.
The external addresses are ignored when ADV/LD is sampled high.
R/W signal is a synchronous input that identifies whether the current load cycle initiated is a
Read or Write access to the memory array. The data bus activity for the current cycle takes
place two clock cycles later.
Synchronous Clock Enable Input. When
CEN
is sampled high, all other synchronous inputs,
including clock are ignored and outputs remain unchang ed. The effect of
CEN
sampled high
on the device outputs is as if the low to high clock transition did not occur. For normal
operation,
CEN
must be sampled low at rising edge of clock.
Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On
load write cycles (When R/W and ADV/LD are samp led low) the appropriate byte write signal
(BW
1
-BW
4
) must be valid. The byte write signal must also be valid on each cycle of a burst
write. Byte Write signals are ignored when R/
W
is sampled high. The appropriate byte(s) of
data are written into the device two cycles later.
BW
1
-BW
4
can all be tied low if always doing
write to the entire 36-bit word.
Synchro nous active low chip enable.
CE
1
and
CE
2
are used with CE
2
to enable the
IDT71V3548. (CE
1
or
CE
2
sampled high or CE
2
sampled low) and ADV/LD low at the rising
edge of clock, initiates a deselect cycle. The ZBT
TM
has a two cycle deselect, i.e., the data
bus will tri-state two clock cycles after deselect is initiated.
Synchronous active high chip enable. CE
2
is used with
CE
1
and
CE
2
to enable the chip. CE
2
has inverted polarity but otherwise identical to
CE
1
and
CE
2
.
This is the clock input to the IDT71V3548. Except for
OE,
all timing references for the device
are made with respect to the rising edge of CLK.
Synchronous data input/output (I/O) pins. Both the data input path and data output path are
registered and triggered by the rising edge of CLK.
Burst order selection input. When
LBO
is high the Interleaved burst sequence is selected.
When
LBO
is low the Linear burst sequence is selected.
LBO
is a static inp ut and it must not
change during device operation.
Asynchronous output enable.
OE
must be low to read d ata from the 71V3548. When
OE
is
high the I/O pins are in a high-impedance state.
OE
does not need to be actively controlled
for read and write cycles. In normal operation,
OE
can be tied low.
Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an
internal pullup.
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This
pin has an internal pullup.
Clo ck input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising
edge of TCK, while test outputs are driven from the falling edge of TCK. This pin has an
internal pullup.
Serial output of registers placed between TDI and TDO. This outp ut is active depending on the
state of the TAP controller.
Optional Asynchronous JTAG reset. Can be used to reset the TAP controller, but not required.
JTAG reset occurs automatically at power up and also resets using TMS and TCK per IEEE
1149.1. If not used
TRST
can be left floating. This pin has an internal pullup.
Synchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the
IDT71V3548 to its lowest power consumption le vel. Data retention is guaranteed in Sleep
Mode. This pin has an internal pulldown
3.3V core power supply.
3.3V I/O Supply.
Ground.
5296 tbl 02
R/W
Read / Write
I
N/A
CEN
Clock Enable
I
LOW
BW
1
-BW
4
Individual Byte
Write Enables
I
LOW
CE
1
,
CE
2
Chip Enables
I
LOW
CE
2
CLK
I/O
0
-I/O
31
I/O
P1
-I/O
P4
LBO
Chip Enable
Clock
Data Input/Output
Linear Burst Order
I
I
I/O
I
HIGH
N/A
N/A
LOW
OE
Output Enable
I
LOW
TMS
TDI
Test Mode Select
Test Data Input
I
I
N/A
N/A
TCK
Test Clock
I
N/A
TDO
Test Data Output
JTAG Reset
(Optional)
O
N/A
TRST
I
LOW
ZZ
V
DD
V
DDQ
V
SS
Sleep Mode
Power Supply
Power Supply
Ground
I
N/A
N/A
N/A
HIGH
N/A
N/A
N/A
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42
2
IDT71V3548, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Functional Block Diagram
LBO
Address A [0:17]
CE1,
CE2,
CE2
R/W
CEN
ADV/LD
BWx
D
Clk
D
Q
Control
D
Q
256x18 BIT
MEMORY ARRAY
Address
Input Register
DI
DO
Q
Control Logic
Mux
Sel
D
Clk
Clock
Output Register
Q
OE
Gate
5296 drw 01
,
TMS
TDI
TCK
TRST
(optional)
JTAG
(SA Version)
Data I/O [0:15],
I/O P[1:2]
TDO
Recommended DC Operating
Conditions
Symbol
V
DD
V
DDQ
V
SS
V
IH
V
IH
V
IL
Parameter
Core Supply Voltage
I/O Supply Voltage
Supply Voltage
Input High Voltage - Inputs
Input High Voltage - I/O
Input Low Voltage
Min.
3.135
3.135
0
2.0
2.0
-0.3
(1)
Typ.
3.3
3.3
0
____
____
____
Recommended Operating
Temperature and Supply Voltage
Unit
V
V
V
V
V
V
5296 tbl 04
Max.
3.465
3.465
0
V
DD
+0.3
V
DDQ
+0.3
(2)
0.8
Grade
Commercial
Industrial
Temperature
(1)
0°C to +70°C
-40°C to +85°C
V
SS
0V
0V
V
DD
3.3V±5%
3.3V±5%
V
DDQ
3.3V±5%
3.3V±5%
5296 tbl 05
NOTES:
1. T
A
is the "instant on" case temperature.
NOTES:
1. V
IL
(min.) = –1.0V for pulse width less than t
CYC
/2, once per cycle.
2. V
IH
(max.) = +6.0V for pulse width less than t
CYC
/2, once per cycle.
6.42
3
IDT71V3548, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration - 256K x 18
CE
2
NC
NC
BW
2
BW
1
CE
2
V
DD
V
SS
CLK
R/W
CEN
OE
ADV/LD
NC
(2)
NC
(2)
A
8
A
9
A
6
A
7
CE
1
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Rating
Terminal Voltage with
Respect to GND
Terminal Voltage with
Respect to GND
Terminal Voltage with
Respect to GND
Terminal Voltage with
Respect to GND
Commercial
Operating Temperature
Industrial
Operating Temperature
Commercial &
Industrial Values
-0.5 to +4.6
-0.5 to V
DD
-0.5 to V
DD
+0.5
-0.5 to V
DDQ
+0.5
-0 to +70
-40 to +85
-55 to +125
-55 to +125
2.0
50
Unit
V
V
V
V
o
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
NC
NC
V
DDQ
V
SS
NC
NC
I/O
8
I/O
9
V
SS
V
DDQ
I/O
10
I/O
11
V
DD
(1)
V
DD
V
DD
(1)
V
SS
I/O
12
I/O
13
V
DDQ
V
SS
I/O
14
I/O
15
I/O
P2
NC
V
SS
V
DDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
10
NC
NC
V
DDQ
V
SS
NC
I/O
P1
I/O
7
I/O
6
V
SS
V
DDQ
I/O
5
I/O
4
V
SS
V
DD
(1)
V
DD
V
SS/ZZ(3)
I/O
3
I/O
2
V
DDQ
V
SS
I/O
1
I/O
0
NC
NC
V
SS
V
DDQ
NC
NC
NC
V
TERM
(3,6)
V
TERM
(4,6)
V
TERM
(5,6)
C
C
C
C
T
A
(7)
o
T
BIAS
T
STG
P
T
I
OUT
Temperature
Under Bias
Storage
Temperature
Power Dissipation
DC Output Current
o
o
,
W
mA
5296 tbl 06
5296 drw 02
Top View
100 TQFP
NOTES:
1. Pins 14, 16 and 66 do not have to be connected directly to V
DD
as long as
the input voltage is
V
IH
.
2. Pins 83 and 84 are reserved for future 8M and 16M respectively.
3. Pin 64 does not have to be connected directly to V
SS
as long as the input
voltage is
V
IL
; on the latest die revision this pin supports ZZ (sleep
mode).
100 Pin TQFP Capacitance
(1)
(T
A
= +25° C, f = 1.0MHz)
Symbol
C
IN
C
I/O
Parameter
(1)
Input Capacitance
I/O Capacitance
Conditions
V
IN
= 3dV
V
OUT
= 3dV
(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. V
DD
terminals only.
3. V
DDQ
terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any input or I/O pin cannot exceed V
DDQ
during power
supply ramp up.
7. T
A
is the "instant on" case temperature.
LBO
A
5
A
4
A
3
A
2
A
1
A
0
NC
NC
V
SS
V
DD
NC
NC
A
11
A
12
A
13
A
14
A
15
A
16
A
17
Max.
5
7
Unit
pF
pF
5296 tbl 07
119 BGA Capacitance
(1)
(T
A
= +25° C, f = 1.0MHz)
Symbol
C
IN
C
I/O
Parameter
(1)
Input Capacitance
I/O Capacitance
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max.
7
7
Unit
pF
pF
5296 tbl 07a
165 fBGA Capacitance
(T
A
= +25° C, f = 1.0MHz)
Symbol
C
IN
C
I/O
Parameter
(1)
Input Capacitance
I/O Capacitance
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max.
TBD
TBD
Unit
pF
pF
5296 tbl 07b
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
6.42
4
IDT71V3548, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration - 256K x 18, 119 BGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
I/O
8
NC
V
DDQ
NC
I/O
11
V
DDQ
NC
I/O
13
V
DDQ
I/O
15
NC
NC
NC
V
DDQ
2
A
6
CE2
A
7
NC
I/O
9
NC
I/O
10
NC
V
DD
I/O
12
NC
I/O
14
NC
I/O
P2
A
5
A
10
NC/TMS
(3)
3
A
4
A
3
A
2
V
SS
V
SS
V
SS
BW
2
V
SS
V
DD(1)
V
SS
V
SS
V
SS
V
SS
V
SS
LBO
A
15
NC/TDI
(3)
4
NC(2)
ADV/LD
V
DD
NC
CE
1
OE
NC(2)
R/W
V
DD
CLK
NC
CEN
A
1
A
0
V
DD
NC
NC/TCK
(3)
5
A
8
A
9
A
13
V
SS
V
SS
V
SS
V
SS
V
SS
V
DD(1)
V
SS
BW
1
V
SS
V
SS
V
SS
V
DD(1)
A
14
NC/TDO
(3)
6
A
16
CE
2
A
17
I/O
7
NC
I/O
5
NC
I/O
3
V
DD
NC
I/O
1
NC
I/O
0
NC
A
12
A
11
NC/TRST
(3,4)
7
V
DDQ
NC
NC
NC
I/O
6
V
DDQ
I/O
4
NC
V
DDQ
I/O
2
NC
V
DDQ
NC
I/O
P1
NC
NC/ZZ(5)
V
DDQ
5296 drw 13
,
Top View
NOTES:
1. J3, J5, and R5 do not have to be directly connected to V
DD
as long as the input voltage is
V
IH
.
2. G4 and A4 are reserved for future 8M and 16M respectively.
3. These pins are NC for the "S" version and the JTAG signal listed for the "SA" version.
4.
TRST
is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to V
DD.
5. Pin T7 supports ZZ (sleep mode) on the latest die revision.
6.42
5
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