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DS1678ST

器件型号:DS1678ST
器件类别:半导体    嵌入式处理器和控制器   
厂商名称:Maxim Integrated
厂商官网:https://www.maximintegrated.com/en.html
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器件描述

0 TIMER(S), REAL TIME CLOCK, PDSO8

DS1678ST器件文档内容

                                                                                            DS1678
                                                                  Real-Time Event Recorder

www.maxim-ic.com                                                  FEATURES

GENERAL DESCRIPTION                                                   Real-Time Clock/Calendar in Binary-Coded
                                                                      Decimal (BCD) Format Counts Seconds,
The DS1678 real-time clock (RTC) event recorder                       Minutes, Hours, Date, Month, Day of the
records the time and date of a nonperiodic,                           Week, and Year with Leap Year
asynchronous event each time the INT pin is                           Compensation and is Year 2000 Compliant
activated. The device records the seconds, minutes,
hours, date, day of the week, month, year, and                        Logs Up to 1025 Consecutive Events in Read-
century when the first event occurs, and starts the 16-               Only Battery-Backed Memory
bit elapsed time counter (ETC). Subsequent events
trigger the recording of the ETC into the event-log                   User-Programmable Event Trigger can be
memory. This allows for up to 1025 events to be                       Triggered by the Falling Edge, Rising Edge,
logged. Events can be logged while the device is                      or Rising and Falling Edges of the INT Pin
operating from either VCC or VBAT.
                                                                      Event Counter Register Provides Data on the
TYPICAL OPERATING CIRCUIT                                             Number of Events that Have Been Logged in
                                                                      the Current Event-Logging Mission

                                                                      Programmable RTC Alarm

                                                                      32-Byte, Battery-Backed, General-Purpose
                                                                      NV RAM

                                                                      I2C* Serial Interface

                                                                      Three Resolution Options for Trade-Off
                                                                      Accuracy vs. Maximum Time Between Events

                                                                      -40C to +85C Industrial Temperature
                                                                      Range

                                                                      Underwriters Laboratory (UL) Recognized

                                                                  ORDERING INFORMATION

                                                                  PART         PIN-PACKAGE TOP MARK

                                                                  DS1678       8 Plastic DIP   DS1678

                                                                  DS1678+      8 Plastic DIP   DS1678

                                                                  DS1678S      8 SO            DS1678S

                                                                  DS1678S+     8 SO            DS1678S

PIN CONFIGURATION                                                 DS1678S/T&R  8 SO (Tape and  DS1678S
                                                                               Reel)
     TOP VIEW
                                                                  DS1678S+T&R  8 SO (Tape and  DS1678S
                                                                               Reel)

  X1  1  DS1678  8  VCC                                            All devices are specified over the -40C to +85C operating
  X2                INT                                           range.
VBAT  2          7  SCL                                            A "`+" anywhere on the top mark denotes a lead-free device.
GND                 SDA                                           + Denotes a lead-free/RoHS-compliant device.
      3          6
                                                                  * I2C is a trademark of Philips Corp. Purchase of I2C components
      4          5
                                                                  from Maxim Integrated Products, Inc., or one of its sublicensed
PDIP (300 mils)                                                   Associated Companies, conveys a license under the Philips I2C
SO (208 mils)                                                    Patent Rights to use these components in an I2C system, provided
                                                                  that the system conforms to the I2C Standard Specification as
                                                                  defined by Philips.

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ABSOLUTE MAXIMUM RATINGS

Voltage Range on Any Pin Relative to Ground.....................................................-0.3V to +6.0V
Operating Temperature Range (noncondensing)...................................................-40C to +85C
Storage Temperature Range.........................................................................-55C to +125C
Soldering Temperature.................................................See IPC/JEDEC J-STD-020 Specification

This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device
reliability.

RECOMMENDED DC OPERATING CONDITIONS

(VCC = VCC(MIN) to VCC(MAX), TA = -40C to +85C, unless otherwise noted. Typical values are at nominal
supply voltage and TA = +25C, unless otherwise noted.) (Note 1)

PARAMETER                    SYMBOL    CONDITIONS         MIN TYP MAX UNITS

Power-Supply Voltage         VCC       (Note 2)           4.5   5.0   5.5     V
Input Logic 1
Input Logic 0                VIH       (Note 2)           2.2         VCC +   V
Pullup Resistor Value         VIL      (Note 2)                        0.3
Battery Voltage              VPU       VCC = 0V (Note 2)
                             VBAT      (Note 2)           -0.3        +0.8    V

                                                                      5.5     V

                                                          2.6         3.5     V

DC ELECTRICAL CHARACTERISTICS

(VCC = VCC(MIN) to VCC(MAX), TA = -40C to +85C.)

PARAMETER                    SYMBOL    CONDITIONS         MIN TYP MAX UNITS

Input Leakage     SDA, SCL        ILI  SDA output off     -1          +1      A
                  INT                  INT output off
                                 VOL                            10
                                 ICCA  VBAT = 3.0V
Logic 0 Output                   VPF                                  0.4     V
IOL = 4mA (SDA, INT)         LOBATTRP
                                                                1     2       mA
Active Supply Current

Power-Fail Voltage (Note 2)                               1.216 1.25 x 1.284  V
                                                          x VBAT VBAT x VBAT

LOBAT Trip Point                                                1.35

DC ELECTRICAL CHARACTERISTICS

(VCC = 0V, TA = -40C to +85C.) (Note 1)

PARAMETER                    SYMBOL    CONDITIONS         MIN   TYP   MAX UNITS
                                                                300
VBAT Current                 IOSC                                     500     nA
(Oscillator On)

VBAT Current                 IBAT                               50    150     nA
(Oscillator Off)

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AC ELECTRICAL CHARACTERISTICS

(VCC= 2.6V to 5.5V or VBAT = 2.6V to 3.5V, TA = -40C to +85C.) (Note 1)

PARAMETER                          SYMBOL CONDITIONS MIN                   TYP  MAX    UNITS
                                                                            10
Input Capacitance                    CI     INT                                 0.245     pF
Minimum Signal Width               tGLITCH                                      1.22     ms
Minimum Event Rate                 tEVENT                  0.122                         ms
                                                           0.854

AC ELECTRICAL CHARACTERISTICS

(VCC = 4.5V to 5.5V, TA = -40C to +85C.) (Note 1)

PARAMETER                          SYMBOL CONDITIONS       MIN TYP              MAX    UNITS
                                                                                 400     kHz
SCL Clock Frequency                 fSCL    Fast mode       100                  100      s
                                    tBUF    Standard mode                                 s
Bus Free Time Between a STOP and   tHD:STA  Fast mode       1.3                  0.9      s
START Condition                     tLOW    Standard mode   4.7                           s
Hold Time (Repeated) START          tHIGH   Fast mode       0.6                  300      s
Condition (Note 3)                 tSU:STA  Standard mode   4.0                 1000      s
                                   tHD:DAT  Fast mode       1.3                  300      ns
LOW Period of SCL                  tSU:DAT  Standard mode   4.7                  300      ns
                                     tR     Fast mode       0.6                           ns
HIGH Period of SCL                    tF    Standard mode   4.0                           s
                                   tSU:STO  Fast mode       0.6
Setup Time for a Repeated START      CB     Standard mode   4.7
                                     CI     Fast mode         0
Data Hold Time (Note 4)                     Standard mode     0
                                            Fast mode       100
Data Setup Time (Note 5)                    Standard mode   250
                                            Fast mode      20 + 0.1CB
Rise Time of Both SDA and SCL               Standard mode  20 + 0.1CB
Signals (Note 6)                            Fast mode      20 + 0.1CB
Fall Time of Both SDA and SCL               Standard mode  20 + 0.1CB
Signals (Note 6)                            Fast mode       0.6
                                            Standard mode   4.0
Setup Time for STOP
Capacitive Load for Each Bus Line                                               400    pF
(Note 6)
Input Capacitance (SCL, SDA)                                               5           pF

WARNING: Under no circumstances are negative undershoots of any amplitude allowed
when the device is in write protect.

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Note 1:  Limits at -40C are guaranteed by design and not production tested.
Note 2:
Note 3:  All voltages referenced to ground.
Note 4:
Note 5:  After this period, the first clock pulse is generated.

Note 6:  A device must initially provide a hold time of at least 300ns for the SDA signal to bridge the undefined region of the falling edge
Note 7:  of SCL. The maximum tHD:DAT need only be met if the device does not stretch the LOW period (tLOW) of the SCL signal.

         A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT > 250ns must then be met. This is
         automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
         period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250ns before the SCL
         line is released.

         CB--Total capacitance of one bus line in pF.

         tR and tF are measured with a 1.7k pullup resistor, 200pF pullup capacitor, 1.7k pulldown resistor, and 5pF
         pulldown capacitor.

I2C COMMUNICATION TIMING DIAGRAM

SDA

         tB U F

                                                                                 tHD:STA

                   tLOW      tR                     tF

SCL                t HD:STA                                                               t SU:STO
       STOP START
                                 t HD:DAT  tH IG H      t SU:DAT  t SU:STA
                                                                      REPEATED
                                                                          START

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BLOCK DIAGRAM

      X1  X2

      CL  CL

                                    1Hz  REAL-TIME
                  DIVIDER                  CLOCK

      OSCILLATOR

                                                        000h     0

INT   CONTROL     ADDRESS                   USER RAM
        LOGIC     REGISTER
                                         DATA LOG RAM
                                                PORT    DATALOG
                                                        NV SRAM

SCL   I2C SERIAL
SDA   INTERFACE

VCC   POWER                                  Dallas    7FFh  2048
VBAT  CONTROL                            Semiconductor
GND
                                            DS1678

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PIN DESCRIPTION

PIN   NAME                                  FUNCTION

                 Connections for Standard 32.768kHz Quartz Crystal. For greatest accuracy,

                 the DS1678 must be used with a crystal that has a specified load capacitance

                 of 12.5pF. There is no need for external capacitors or resistors. Note: X1 and

1, 2  X1, X2 X2 are very high-impedance nodes. It is recommended that they and the

                 crystal be isolated from high-frequency signals. For more information on

                 crystal selection and crystal layout considerations, refer to Application Note

                 58: Crystal Considerations with Dallas Real-Time Clocks.

                 Battery Input for Standard Lithium Cell or Other Energy Source. All

                 functions of the DS1678 with the exception of the serial interface circuitry

                 are powered by VBAT when VCC < VBAT. All functions are powered by VCC

                 when VCC > VBAT. The serial interface is enabled when VCC is above VPF. If

3     VBAT a battery or other energy source is not used, VBAT should be connected

                 directly to ground. Diodes must not be placed between the battery and the

                 VBAT input or improper operation results. UL recognized to ensure against
                 reverse charging current when used with a lithium battery. See "Conditions

                 of Acceptability" at www.maxim-ic.com/qa/info/ul/.

4     GND Ground

                 Serial Data Input/Output. SDA is the data input/output (I/O) signal for the

5     SDA I2C serial interface. The SDA pin is an open-drain I/O and requires an

                 external pullup resistor.

6     SCL        Serial Clock Input. SCL is used to synchronize data movement on the serial
                 interface. It requires an external pullup resistor.

                 Active-Low Interrupt Input/Output. The INT pin is an I/O that is activated by
                 an external device to signify an event has occurred and should be logged.
                 Once the pin is activated, the event is recorded in the event-log memory and
                 the Event Counter Register is incremented. The TRx bits determine which
                 input edge(s) trigger an event: An event can be triggered by a falling edge on
                 the INT pin, a rising edge, or by both the rising and falling edges.

7     INT The INT pin can also be used as an output when the DS1678 is not in an

                 event-logging mission. The INT pin becomes an output and generates an

                 alarm interrupt if the DISx bits are set to zero and the RTC reaches the preset

                 value in the alarm register. The INT output remains low as long as the status

                 bit causing the interrupt is present and the DISx bits are set to zero.

                 The INT pin is an open-drain input/output with a weak internal pulldown
                 resistor to prevent the pin from floating when the pin is tri-stated.

8     VCC DC Power for Primary Power Supply

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DETAILED DESCRIPTION

The Event Counter Register contains the total number of events that have been logged in the current
event-logging mission. The Event Counter Register also allows the user to determine if the data in the
event-log memory has rolled over.

The 16-bit ETC can be incremented once per second, once per minute, or once per hour. Each event
transfers the current ETC value into the event-log memory, then clears and restarts the ETC. The three
increment periods allow users to maximize the resolution while providing an adequate maximum time
between events. The seconds resolution provides the time of an event down to the second, while allowing
up to 65,535 seconds (18.2 hours) between events without using additional event-log memory. The
minutes resolution provides the time of an event down to the minute, while allowing up to 45.5 days
between events without using extra memory locations. The hours resolution provides the time of an event
down to the hour in which it occurred, while allowing up to 7.5 years between events without using
additional event-log memory. Based on the expected frequency of events, an increment period can be
selected to maximize the resolution while minimizing use of the event-log memory.

The event can be triggered in three different ways depending on how the user programs the trigger select
(TRx) bits in the Control Register. The event can be triggered by a falling edge on the INT pin only, a
rising edge only, or it can be triggered by rising and falling edges. Triggering with both the rising and
falling edges allows for monitoring when something is turned on/off and how long it is in either state.

The RTC provides seconds, minutes, hours, day, date, month, and year information with leap-year
compensation, and year 2000 compliance. The RTC also provides an alarm interrupt. The I2C interface
allows the RTC to function as a stand-alone RTC in the system.

The programmable alarm trip points in the RTC allow a flag to be set in the Control Register when the
specified time in the Alarm Trip Point Register is reached. The flag is readable via the I2C interface
during an event-logging mission or, when the DS1678 is not in a mission, INT becomes an output and
generates an alarm interrupt if the value in the RTC equals the value in the RTC Alarm Register and the
duration interval select (DISx) bits are both set to zeros.

The DS1678 operates as a slave device on the I2C serial bus. Access is obtained by generating a START
condition and providing a device identification code. All data is transferred to and from the DS1678 most
significant bit (MSB) first. The address counter automatically increments so that subsequent registers can
be accessed sequentially until a STOP condition is executed. When VCC falls below 1.25 x VBAT, the
device automatically write protects itself by disabling the I2C interface, terminates any access in progress,
and resets the device address counter. Inputs to the device via the I2C bus are not recognized at this time
in order to prevent erroneous data from being written to the device from an out-of-tolerance system.
When VCC falls below VBAT, the device switches into a low-current battery-backup mode. Upon power-
up, the device switches from battery power to VCC when VCC is greater than VBAT + 0.2V, and recognizes
inputs from the system when VCC is greater than 1.25 x VBAT by releasing control of the write protection
on the I2C bus.

The Block Diagram shows the main elements of the RTC event recorder. The device has four major
components: a 64-bit RTC and control block, 32-byte user NV RAM, 2048 bytes of event-log memory
(1024 events), and an I2C serial interface.

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POWER CONTROL

The device is fully accessible and data can be written and read when VCC is greater than VPF. However,
when VCC falls below VPF, the internal registers are blocked from any access. The device power is
switched from VCC to VBAT when VCC drops below VBAT. Operation, except for the I2C interface, is
maintained from the VBAT source until VCC is returned to nominal levels (Table 1). After VCC returns
above VPF, read and write access is allowed.

Table 1. Power Control

        SUPPLY          READ/WRITE        POWERED
     CONDITION             ACCESS              BY
VCC < VPF, VCC < VBAT           No            VBAT
VCC < VPF, VCC > VBAT           No             VCC
VCC > VPF, VCC > VBAT          Yes             VCC

OSCILLATOR CIRCUIT

The DS1678 uses an external 32.768kHz crystal. The oscillator circuit does not require any external
resistors or capacitors (CL) to operate. Table 2 specifies several crystal parameters for the external crystal,
and the oscillator block in the Block Diagram shows a functional schematic of the oscillator circuit. Using
a crystal with the specified characteristics, the startup time is usually less than one second.

Table 2. Crystal Specifications*

PARAMETER SYMBOL MIN TYP MAX UNITS

Nominal Frequency       fO                32.768                    kHz

Series Resistance       ESR                                     45  k

Load Capacitance        CL                12.5                      pF

*The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to

Application Note 58: Crystal Considerations for Dallas Real-Time Clocks for additional specifications.

CLOCK ACCURACY

The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match
between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was
trimmed. Additional error is added by crystal frequency drift caused by temperature shifts. External
circuit noise coupled into the oscillator circuit can result in the clock running fast. Figure 1 shows a
typical PC board layout for crystal and oscillator isolation from noise. Refer to Application Note 58:
Crystal Considerations with Dallas Real-Time Clocks for detailed information.

Figure 1. Typical Crystal Layout

         LOCAL GROUND PLANE (LAYER 2)

                                      X1
CRYSTAL

                                      X2

                            GND

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MEMORY

The memory map in Figure 2 shows the general organization of the DS1678. As can be seen in the figure,
the device memory is in one contiguous segment with a data port to access the event-log memory.
Because the I2C bus is limited to a maximum of 256 addresses (one byte), the DS1678 uses the data port
to access the 2048 bytes of event-log memory. The address that the next data would have been written to
before logging was stopped is stored in the Address Pointer Register LSB (3Fh) and MSB (40h). These
data bytes are used to recover all the data after a rollover occurs. The data log address pointer points to
the oldest event in the memory after a rollover. This is the memory location in event-log memory that
would be overwritten by the next event. Read the data from this point to the end of the memory and the
start time stamp, including the two-byte ETC from the last event. Working backward from the value in
the start time stamp, subtract the value in the ETC from the last event to get the time the last event in the
memory occurred. Then subtract the values in each of the two-byte memory locations for elapsed time
between events to recover the time the previous event occurred.

The value in the ETC register LSB (3Dh) and MSB (3Eh) is the value in the actual ETC. This is the time
from the last event recorded until logging was stopped. Since a new event has not occurred, this data has
not been stored in the event memory yet.

The data port is made up of three bytes. The first byte (41h) is the event-log memory address LSB, the
second byte (42h) is the event-log memory address MSB, and the third byte (43h) is the event-log
memory data byte. To access data via the data port, an I2C write to the LSB of the event log LSB (41h) is
performed, writing the appropriate LSB address information. The I2C register pointer automatically
increments to the event-log memory address MSB (42h), where a second I2C write is performed, writing
the MSB address information. The I2C register pointer automatically increments to the event-log data
byte address (43h). A repeated start, followed by the I2C slave address with a read command (1) in the
R/W bit of the I2C address byte is performed. Subsequent read cycles reads the event-log information in
the event-log memory.

For each read, the event-log memory address pointer in main memory locations 41h and 42h is
autoincremented to the next higher event-log memory address, while the pointer for the main memory
remains at location 43h. This allows the event-log memory to be read continuously without having to
write the next desired event-log memory location prior to each data read. The even address locations in
the event-log memory correspond to the LSB of the elapsed time between events, and the odd memory
locations correspond to the MSB of the elapsed time between events. See Table 3 for more information
about how the data is stored in the event-log memory.

When the event-log memory address pointer gets to the last address location (07FFh), the automatic
incrementing stops. A new starting address must then be written into the event-log memory pointer bytes
(41h and 42h) to begin reading additional data. The event-log memory addresses that can be put into the
pointer (41h and 42h) are 0000h to 07FFh. The five MSBs of the address are ignored. Entering a value
greater than 07FFh results in the address location associated with the value of the lowest 11 bits of the
address.

The RTC and control registers (see Figure 2 for more details) are located in the main memory between
addresses 00h and 0Fh. The user NV RAM resides in locations 10h through 2Fh. The event-logging
memory data port is located at locations 41h, 42h, and 43h. Memory locations 44h and up are reserved for
future extensions and read 00h.

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The user can write only to the RTC, control registers, and user NV RAM. The rest of the memory map is
read-only from the user's perspective. During an event-log mission, all the memory is read-only. A write
terminates the mission. If there is an event being recorded when the mission is terminated, the event
finishes being recorded before the mission is stopped, and the values in the MIP and ME bits do not
change to zeros until the mission is complete.

During an event-log mission, memory locations 30h and above are not accessible to the user to avoid data
collisions from a user read and an event being logged at the same time. If the user tries to read a location
with an address greater than 2Fh during a mission, the value returned is 00h.

Table 3. DS1678 Event Elapsed Time Duration

ADDRESS                              REGISTER
    0000  Event 1 Elapsed Time from Last Event Counter LSB
    0001  Event 1 Elapsed Time from Last Event Counter MSB
    0002  Event 2 Elapsed Time from Last Event Counter LSB
    0003  Event 2 Elapsed Time from Last Event Counter MSB
    0004
               
   07FB
   07FC   Event 1023 Elapsed Time from Last Event Counter LSB
   07FD   Event 1023 Elapsed Time from Last Event Counter MSB
   07FE   Event 1024 Elapsed Time from Last Event Counter LSB
   07FF   Event 1024 Elapsed Time from Last Event Counter MSB

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Figure 2. DS1678 RTC and Control Page

ADDRESS  MSB    BIT 6 BIT 5 BIT 4                BIT 3     BIT 2 BIT 1             LSB      FUNCTION
     00  BIT 7                                     0           Seconds             BIT 0
     01                                                        Minutes                           RTC
           0           10 Seconds
     02    0                                                                                 RTC Alarm
                          10 Minutes                       Hour
     03    0    12/24 AM/PM 10 Hr                                                             Reserved
     04                                                                                        Control
     05    0                 10 Hr                                                              Status
     06    0                                                                                    User-
     07    0    0               0           0                  Day of Week                 Programmable
                                                             Date                           NV Memory
                0                  10 Date                 Month
                                                            Year                            Time Stamp
                0      0           10 Mo                   Century
                                                                                          Event 0 Rollover
                       10 Year                                                                  Stamp

                   10 Century                                                              Event Counter
                                                                                           Elapsed Time
08       MS        10 Seconds Alarm                        Seconds Alarm                   Counter (ETC)
                                                                                          Address Pointer
09       MM        10 Minutes Alarm                        Minutes Alarm                  Data Log RAM
                                                            Hour Alarm
0A       MH     12/24  AM/PM       10 Hr                                                         Port
                        10 Hr                                                                 Reserved

0B       MD     0               0           0           0  Day-of-Week Alarm

0C                                          (Reads 00h)

0D

0E       ME CLR DIS1 DIS0                              RO  TR1 TR0 EOSC

0F       0      MEM    MIP           CM LOBAT ROF                        0         ALMF
                CLR

10                                             Byte 1

11                                             Byte 2

12                                             Byte 3

                                               

2F                                             Byte 32

                Higher addresses read back as 00h while a mission is in progress.

30       0             10 Seconds                          Seconds

31       0             10 Minutes                          Minutes
                                                            Hours
32       0      12/24 AM/PM 10 Hr
                       10 Hr

33       0      0               0           0          0   Day-of-Week

34       0      0                  10 Date                 Date

35       0      0               0  10 Mo                   Month

36                     10 Year                             Year

37                 10 Century                              Century

38                     Event 0 Elapsed Time from Last Event Counter LSB

39                     Event 0 Elapsed Time from Last Event Counter MSB

3A                                             Low Byte

3B                                          Medium Byte

3C                                             High Byte

3D                                             Low Byte

3E                                             High Byte

3F                                 Low Address Byte

40                                 High Address Byte

41                                 Low Address Byte

42                                 High Address Byte

43                                             Data Byte

44

                                            (Reads 00h)

FF

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                                                                                                              DS1678 Real-Time Event Recorder

EVENT LOGGING

When the DS1678 event-logging function is enabled, the device is said to be on an "event-log mission"
until the event logging is stopped.

An event can be triggered one of three ways depending on the settings of the TRx bits in the Control
Register. With the TR0 bit set to one and the TR1 bit set to zero, INT is activated on the falling edge of
the input signal. With the TR0 bit set to zero and the TR1 bit set to one, INT is activated on the rising
edge of the input signal. With both TR0 and TR1 bits set to one, INT is activated on both the falling and
rising edges to allow for the measurement and duration of on/off type events. If TR0 and TR1 are both set
to zero, nothing happens when INT is toggled, and a mission does not start. This is an illegal state and the
mission does not start without a valid value in the TRx bits prior to attempting to start the mission.

During an event-log mission, every time INT is activated, the elapsed time from the last event is written
to the event-log memory pages. These memory pages are accessible through the data port in the main
memory. To access data via the data port, the LSB of the address location in the event-log memory is
written into 41h, the main memory address pointer automatically increments to 42h where the event-log
memory address MSB data is written. The data from the event-log memory location corresponding to the
address written into main memory locations 41h and 42h is available in location 43h to be read. The
event-log data is located at addresses 0000h07FFh in the event-log memory. The LSB of the first event
duration is written to address location 0000h. The MSB of the first event duration is written to address
location 0001h. The LSB of the second event is written to address location 0002h. The MSB of the
second event duration is written to address location 0003h (see Table 3 for more details). Likewise, the
address is incremented with each additional event duration. A total of 2048 registers have been reserved
for event-log data, which allow 1024 events to be logged.

An event-log mission can be initiated by two methods (Figure 3). The first method to start a mission is
with a delayed start. This is accomplished by writing a one to the ME bit. The mission starts when the
first event occurs by activating INT. When INT is activated, the MIP bit in the Status Register is set to
one, the current time/date is written to the Start Time Stamp Register, and the Event 0 Rollover Stamp is
written to zero. The Event Counter Register is incremented and the ETC starts. Subsequent events are
logged as the duration of time from the previous event by writing the contents of the ETC into the event-
log memory when that subsequent event is triggered by the activated INT pin. Note: The ME bit can only
be written to one and a mission started if the MEM CLR bit is set to one.

The second way to start a mission is write a one to the MIP bit of the Status Register over the I2C
interface. When MIP is written to one, the ME bit in the Control Register is automatically set to one.
When the MIP bit is written to one, the mission is started by loading the current time/date into the start
time stamp, and the Event 0 Rollover Stamp is written to zero. The Event Counter Register is
incremented and the ETC starts incrementing. The first event is then logged as the duration of time since
the start time. All subsequent events are then logged as the duration of time since the previous event.
Note: The MIP bit can only be written to one and a mission started if the MEM CLR bit is set to one.

The MEM CLR bit of the Status Register must be a one to start an event-log mission. This means that the
Event-Log Memory, Event Count, ETC, Address Pointer, and Start Time Stamp registers are cleared of
data (all zeros) so that an end user cannot turn the logger on and off to avoid recording events. Once the
mission is stopped, the memory must be cleared to start a new mission.

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Figure 3. Start Mission Flow Chart                                     DS1678 Real-Time Event Recorder

                          Start via                   Start via
                         Computer                 External Event

                     no   Clear                                        no      Clear
Mem Clr =1               Memory                   Mem Clr =1                  Memory

             yes                                               yes

   Write a 1 to                                   Write a 1 to
   the MIP bit                                    the ME bit.

  The ME bit is                                     MIP = 0
  Automatically
  Written to a 1                                                      no       Continue to
                                                  INT Input                   Monitor Input
Time/Date Stamp                                   Activated
    is Written
                                                              yes
    ETC Starts
  Incrementing                                    MIP Automatically
                                                     Written to a 1
       EC is
   Incremented

                    no    Continue to             Time/Date Stamp is
INT Input                Monitor Input                   Written
Activated
                                                        ETC Starts
            yes                                       Incrementing.

                                                           EC is
                                                       Incremented

Record Event in                                                           no   Continue to
Event Memory                                          INT Input               Monitor Input
                                                      Activated
     ETC is
     Cleared                                                      yes

                                                  Record Event in
                                                  Event Memory

                                                       ETC is
                                                       Cleared

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                                                                                                              DS1678 Real-Time Event Recorder

ROLLOVER HANDLING

There are two options for dealing with the potential occurrence of a data overrun (i.e., more than 1024
total event logs in the event-log memory) (Figure 4). The first option is to enable rollovers. This is
accomplished by setting the rollover bit (bit 3 of the Control Register) to one. When rollover is enabled,
new data is written over previous data, starting with the Start Time Stamp Register, as if a new mission is
starting.

When a rollover occurs, the Event 0 Rollover Stamp has the elapsed time since event 1024 of the event-
log memory. This is to allow the user to recover the information recorded prior to the rollover. At the start
of a mission, the Event 0 Rollover Stamp data is zero, as there was no previous event from which to have
an elapsed time.

When 1024 events are recorded in the event-log memory, the next event causes a new time/date stamp to
be written to the Start Time Stamp Register and the elapsed time since event 1024 written to the event 0
rollover stamp. The new event is written to the first location in the event log, overwriting the old data, and
the address pointer is incremented. When the rollover occurs, the rollover flag (ROF) in the Control
Register is set to one to indicate that the memory has rolled over at least one time.

The second option for dealing with data overrun is to disable rollovers by setting the rollover bit to 0. The
DS1678 stops recording after event 1025, and the address pointer is incremented from 07FFh to 0000h.
The device continues monitoring INT and the event counter continues to increment when INT is
activated, even though the event-log memory has been filled.

A time stamp for the first event is recorded after a mission begins. The time of acquisition for subsequent
events is determined by considering the start time recorded by the time stamp; the value in the Event
Counter Register, ROF; and the address of the particular data sample in the event-log memory.

If no rollover has occurred in the event-log memory (ROF = 0), the sample time associated with any
particular data point can be calculated by multiplying the sum of the elapsed time between the events up
to that event by one second, minute, or hour depending on which resolution is selected in the DISx bits of
the Control Register, and adding this elapsed time to the value in the Start Time Stamp Register.

If rollover has been enabled, the user can determine if rollover has occurred by reading the value in the
Event Counter Register or the ROF. The Event Counter Register counts the total number of events that
have been acquired. If this value is greater than 0400h (decimal 1025), then the user knows that rollover
has occurred. If rollover has occurred, the user needs to determine how many times rollover occurred in
determining the sample time for any particular data sample. The address pointer points to the oldest data
in the event-log memory, and, if the memory has rolled over at least one time, the rollover flag is set to
one.

The DS1678 has been designed so the user cannot directly write to the event-log memory. This prevents
writing invalid data to the event-log registers.

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                                                  DS1678 Real-Time Event Recorder

Figure 4. Rollover Flow Chart

    EC is
Incremented

                     no           Continue to
INT Input                        Monitor Input
Activated

           yes

                             no  Record Event in
        Memory                   Event Memory

           Full

                  yes

                             no
        Rollover
       Enable = 1

                   yes

ETC Written to Event 0
            and

   Time/Date Stamp
        is Written

ETC is
Cleared

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                                              DS1678 Real-Time Event Recorder

CLOCK, CALENDAR, AND ALARM

The time and calendar information is accessed by reading/writing the appropriate register bytes. Note that
some bits are set to zero. These bits always read zero regardless of how they are written. The contents of
the time, calendar, and alarm registers are in the BCD format and are year 2000 compliant.

The DS1678 can run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the 12- or
24-hour mode select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the
AM/PM bit with logic one being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (2023 hours).
The day register increments at midnight. Values that correspond to the day of week are user defined, but
must be sequential, e.g., if 1 equals Sunday, then 2 equals Monday, and so on. Illogical time and date
entries result in undefined operation.

When reading or writing the time and date registers, secondary (user) buffers are used to prevent errors
when the internal registers update. When reading the time and date registers, the user buffers are
synchronized to the internal registers on an I2C start. The time and calendar information is read from
these secondary registers, while the clock continues to run. The countdown chain is reset whenever the
seconds register is written. Write transfers occur on the acknowledge from the device. Once the
countdown chain is reset, to avoid rollover issues the remaining time and date registers must be written
within one second.

The DS1678 also contains a time-of-day alarm. The alarm registers are located in registers 08h0Bh. Bit
7 of each of the alarm registers is a mask bit (Table 4). When all the mask bits are logic zero, an alarm
occurs once per week when the values stored in timekeeping registers 00h03h match the values stored in
the time-of-day alarm registers. An alarm is generated every day when the mask bit of the day alarm
register is set to one. An alarm is generated every hour when the day and hour alarm mask bits are set to
one. Similarly, an alarm is generated every minute when the day, hour, and minute alarm mask bits are set
to one. An alarm occurs every second when the day, hour, minute, and seconds alarm mask bits are set to
one. As a security measure to prevent unauthorized tampering, writing to any memory location or
changing any value in the RTC and control registers stop an event-log mission and clear the MIP bit to
zero.

Table 4. Time-of-Day Alarm Bits

ALARM REGISTER MASK BITS (BIT 7)

SECONDS MINUTES HOURS DAYS                               DESCRIPTION

(MS)  (MM)  (MH) (MD)               Alarm once per second
                                    Alarm when seconds match
1     1     1                    1  Alarm when minutes and seconds match
                                    Alarm when hours, minutes, and seconds match
0     1     1                    1  Alarm when day, hours, minutes, and seconds match

0     0     1                    1

0     0     0                    1

0     0     0                    0

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SPECIAL-PURPOSE REGISTERS

The following descriptions define the operation of the DS1678 special-purpose registers.

CONTROL REGISTER (0Eh)

MSB                                                                                 LSB
                                                                                   BIT 0
BIT 7  BIT 6  BIT 5     BIT 4  BIT 3     BIT 2                              BIT 1  EOSC
                        DIS0    RO        TR1                                TR0
ME     CLR    DIS1

Bit 7: Mission Enable (ME). This bit enables the device to begin a mission. The ME bit cannot be
written to one unless the MEM CLR bit in the Status Register is one, signifying that the memory and
registers have been cleared. With the ME bit set to one, the device waits for the first event to occur (INT
is activated). Once that first event occurs, the MIP bit is set, the time/date stamp is recorded in the Start
Time Stamp Register, the Event 0 Rollover Stamp is written to zero, the Event Counter Register is
incremented, and the ETC begins incrementing.

When the ME bit is set to logic zero, the DS1678 waits until a one is written to the MIP bit via the I2C
interface to start the mission. When the MIP bit is written to one, the ME bit is set to one, the current
time/date is recorded in the Start Time Stamp register, the Event 0 Rollover Stamp is written to zero, the
Event Counter Register is incremented, and the ETC begins incrementing.

The ME bit is automatically written to zero whenever a mission is stopped.

Bit 6: Clear Enable (CLR). This bit enables the memory to be cleared. When this bit is set to logic one
and the clear memory (CM) bit is subsequently set to one, the Event-Log Memory, Event Counter, and
Start Time Stamp registers are all cleared to zeros. Following the writing of a one to the ME bit, the CLR
bit is also set to logic zero, and the MEM CLR bit is set to logic one. If the clear enable bit is set, but a
command other than writing a one to the clear memory bit is issued next, the CLR bit is cleared to zero
and the contents of the Event-Log, Start Time Stamp, and Event Counter registers are unchanged.

Bits 5 and 4: Duration Interval Select 1 and 0 (DIS1 and DIS0). These bits select the amount of time
between increments of the ETC that is used to determine the amount of time between events. After the
first event is recorded, all subsequent events are recorded as the elapsed time since the previous event.
When a subsequent event occurs, the ETC value is stored in the event-log memory.

To obtain the maximum accuracy of the event logger, the smallest possible resolution of the ETC should
be selected. The expected maximum time between events must also be taken into account to get the full
1025 events logged, because when the ETC count reaches 65,535 increments, if the next event has not
occurred by that point, FFFFh is written into the memory, the ETC rolls over to 0000h and continues to
count until the next event occurs or FFFFh is reached again. Whenever FFFFh is reached by the ETC, it
stores that value in event-log memory, resets to 0000h, continues counting, and the memory address
pointer increments to the next memory location. Whenever an FFFFh appears in the memory, the next
two bytes of data are part of the elapsed time for the same event, even if the value in the next two bytes of
memory are 0000h, which means that an event occurred at time increment FFFFh. To recover the total
elapsed time between events when FFFFh is in the event-log memory; add the contents of the next two
bytes to the FFFFh. If the next two bytes are 0000h, indicating that the event occurred at FFFFh, add the
0000h to FFFFh to get FFFFh. If the next two bytes are 0100h, add 0100h to FFFFh to get 100FFh. This

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                                                                                                              DS1678 Real-Time Event Recorder

represents the total elapsed time since the previous event. The event counter is not incremented when the
ETC rolls over because a new event has not occurred.

The ETC is incremented as the selected seconds, minutes, or hours register of the RTC increments.
Because the RTC continues to run, even when the ETC is cleared to prepare for a new event, and the ETC
is incremented every time the selected byte in the RTC increments, the actual time resolution is not lost
even when events occur more frequently than the minimum time resolution selected. If an event occurs
half way between increments of the ETC, the first increment of the next event occurs when the seconds,
minutes, or hours register increments next, thus preserving the correct time to the resolution selected in
the DISx bits.

When the alarm interrupt output is used, the DISx bits should be set to zeros. An event-logging mission

cannot be started if the DISx bits are set to zero. This enables the alarm flag to generate an alarm interrupt
via the INT output pin.

With the DIS0 bit set to one and the DIS1 bit set to zero, the ETC increments every time the seconds
register in the RTC is incremented. This gives the maximum resolution between events, but the counter
rolls over to the next two memory bytes when it reaches the maximum value. The largest interval between
events that can be accurately measured without using additional memory space and reducing the total
number of events able to be logged is 65,535 seconds, or about 18.2 hours. If the maximum time between
events could be greater than 18.2 hours, consider using one of the courser resolutions to conserve
memory.

With the DIS0 bit set to zero and the DIS1 bit set to one, the ETC increments every time the minutes
register in the RTC is incremented. This gives a medium resolution between events, but increases the
largest possible interval between events that can be accurately measured without using additional memory
space and reduces the total number of events able to be logged to 65,535 minutes, or about 45.5 days.

With both DISx bits set to one, the ETC increments every time the single hours byte in the RTC is
incremented. This gives the lowest resolution between events, but increases the largest possible interval
between events that can be accurately measured without using additional memory space and reduces the
total number of events able to be logged to 65,535 hours, or about 7.5 years.

If a second event occurs before the ETC is able to increment for the first time, all zeros are logged in the
event-log memory and the ETC resets. If this occurs, the time base remains correct as it is based on the
separate RTC incrementing, but the exact time of the event is no more accurate than the size of the time
increment that is chosen. For this reason, it is recommended to use the finest resolution possible for your
logging to minimize the errors. If the normal duration between events is several days or months, then a
few minutes or an hour may not be significant to your data accuracy.

Table 5. Duration Interval Select Bits

DIS1  DIS0      ELAPSED TIME COUNT                 MAX TIME
                       RESOLUTION            BETWEEN EVENTS
  0     0
  0     1   Alarm Interrupt Output Enabled               --
  1     0   Counter Increments Every Second         18.2 Hours
  1     1   Counter Increments Every Minute         45.5 Days
            Counter Increments Every Hour            7.5 Years

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                                                                                                              DS1678 Real-Time Event Recorder

Bit 3: Rollover (RO). This bit determines whether the data log function of the DS1678 rolls over or stops
writing data to the event-log memory if the event-log memory is completely filled. If RO is set to one, the
event-log memory rolls over after all 2048 bytes in the event-log memory have been used. After the
1024th event recorded in the event-log memory, the following sample has the full time/date stamp
information written to the Start Time Stamp register and the contents of the ETC written to the two bytes
following the start time stamp (Event 0 Rollover Stamp). The next sample has the duration of time from
the new start time stamp value written to event-log memory address locations 0000h and 0001h,
overwriting the original data. Likewise, subsequent samples increment through the event-log registers,
overwriting their data.

The Event 0 Rollover Stamp has the elapsed time since the last event in the event-log memory. This is to
allow the user to recover the information prior to the rollover. At the start of a mission, the value in these
two bytes is zero since there was no previous event from which to have an elapsed time.

If RO is set to zero, no further event logs are written to the event-log memory after all event-log memory
registers have been filled. However, events continue to be recognized, and the Event Counter Register is
incremented for each event.

Bits 2 and 1: Trigger Select 0 and 1 (TR1 and TR0). These bits select the edge(s) that activate INT to

cause an event to be logged. An event can be triggered one of three ways, depending on the settings of the
TRx bits in the Control Register. With TR0 set to one and TR1 set to zero, INT is activated on the falling
edge of the input signal. With TR0 set to zero and TR1 set to one, the INT is activated on the rising edge

of the input signal.

With TR0 and TR1 set to zero, INT is activated by the rising and falling edges to allow for the
measurement and duration of on/off type events. If TR0 and TR1 are set to zero, nothing happens when
INT is toggled, and a mission does not start. This is an illegal state, and the mission does not start without
a valid value in the TRx bits prior to attempting to start the mission.

Table 6. Trigger Select Bits

TR1 TR0    EDGE(S) USED TO
         TRIGGER AN EVENT

0  0 Nothing, Illegal State

0  1 Falling Edge

1  0 Rising Edge

1  1 Both Rising and Falling Edges

Bit 0: Enable Oscillator (EOSC). This bit allows the clock oscillator to shut off to save power. The RTC
no longer keeps time when the oscillator is shut off, but the information stored in the device memory is
maintained. An event-log mission cannot start with EOSC set to zero, and the RTC must be reset to the
correct value after the oscillator is restarted and prior to starting a mission to obtain good data. A clear
memory also cannot be executed without the oscillator running. When VCC > VBAT, the oscillator
automatically starts, no matter what the value in the EOSC bit, to allow proper communications.
Disabling the oscillator with EOSC can be used to extend the battery life whenever time and date
operation on battery backup is not required.

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                                               DS1678 Real-Time Event Recorder

STATUS REGISTER (0Fh)

MSB                                                    LSB
                                                      BIT 0
BIT 7  BIT 6  BIT 5    BIT 4   BIT 3    BIT 2  BIT 1  ALMF
                        CM    LOBAT     ROF      0
0      MEM CLR MIP

Bit 6: Memory Cleared (MEM CLR). This bit indicates that the Event-Log Memory, Event Counter,
and Start Time Stamp registers are all cleared to zero. MEM CLR is cleared to zero when an event-log
mission is started (i.e., MIP = 1).

Bit 5: Mission in Progress (MIP). This bit indicates the sampling status of the DS1678. If MIP is logic

one, the device is currently on a "mission" in which it is operating in the event-logging mode. The MIP
bit is changed to logic one immediately following the activation of INT if the ME bit of the Control
Register contains a one. To immediately start an event-logging mission via the I2C bus, a one can be

written into the MIP bit and a one is automatically written into the ME bit of the Control Register.

If MIP is logic zero, the DS1678 is not currently in event-logging mode. The MIP bit transitions from
logic one to logic zero whenever event logging is stopped. Event logging is stopped when the DS1678 is
cleared by writing to the clear enable and memory clear bits, or when any memory location including the
RTC or control registers is written to during a mission. The MIP bit can also be written to logic zero by
the end user to stop event logging via the I2C bus. By writing a zero to the MIP bit and stopping the
mission, a zero is automatically written to the ME bit of the Control Register. It cannot, however, be
written to logic one to start a mission unless the MEM CLR bit is a one to signify that the memory has
been cleared.

Bit 4: Clear Memory (CM). This bit triggers the memory to be cleared if the CLR clear enable and
EOSC oscillator enable bits in the Control Register are set to one. This causes the Event-Log Memory,
Event Counter, and Start Time Stamp registers to all be cleared to zeros. Once the memory has been
cleared, the CLR enable bit and the CM bits are set to zeros, and the MEM CLR bit is set to one to allow
a new mission to begin. Clearing the memory is a two-write process to reduce the risk of accidentally
erasing the memory. The CLR bit must be set to one before the CM bit can be written to one. During the
clear memory operation, the DS1678 should not be accessed for 500s while the memory is erased. The
MEM CLR bit should read a one before trying to access the cleared memory or registers.

Bit 3: Low-Battery Flag (LOBAT). This bit reflects the status of the backup power source connected to
the VBAT pin. A logic one for this bit indicates an exhausted lithium energy source.

Bit 2: Rollover Flag (ROF). This bit is set to one if the RO bit of the Control Register is set to one, the
last data log memory location has been filled, and a new event has occurred, which causes the time/date
stamp to be overwritten. If RO is set to zero (rollover is disabled), the last data log memory location has
been filled, and a new event has occurred, ROF is set to one to indicate that more events have occurred
than the number of available memory locations. The event counter continues to record events, even after
the event-log memory is full. The ROF is cleared by the clear memory command.

Bit 0: Alarm Flag (ALMF). A logic one in the alarm flag bit indicates that the current time has matched
the time-of-day alarm registers. If, at the same time, the DISx bits are both logic zero, INT goes low to
issue an alarm interrupt. ALMF is a read-only bit and is cleared by accessing any of the Alarm Register
bytes either with a read or a write. Writing any memory location during a mission stops the mission. A
mission cannot be started when the DISx bits are set to zero.

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                                                                          DS1678 Real-Time Event Recorder

EVENT COUNTER REGISTER (3Ah3Ch)

This three-byte register set provides the number of events that have been logged during the current data-
logging operation (also known as a "mission"). The contents of this register can be used by software to
point to the most recent data sample in the event-log memory. The data in these registers are cleared
when the event-log memory is cleared. The event counter is not incremented when the ETC reaches
FFFFh and rolls over to the next 16 bits of memory.

ADDRESS POINTER REGISTER (3Fh40h)

The address pointer register always contains the address that the next data LSB is written to in the event-
log memory. The address pointer registers are located in the main memory map at LSB (3Fh) and MSB
(40h). These are helpful in recovering all the data if a rollover occurs. The address pointer points to the
oldest event in the memory after a rollover. This is the memory location that would be overwritten by the
next event. Read the data from this point to the end of the memory and the start time stamp, including the
two-byte ETC from the last event to recover all the data in the correct order.

GLITCH-CONTROL CIRCUIT

The DS1678 has a built-in glitch-control circuit to filter noise on INT from triggering false events. A
minimum of one internal clock cycle (0.122ms) up to a maximum of two internal clock cycles (0.245ms)
are required to recognize a transition on the input as an event. An event then requires an additional six to
eight internal clock cycles (0.752ms to 0.977ms) to be processed and recorded into memory. This means
that the minimum event occurrence that can be recognized by the DS1678 requires seven to 10 internal
clock cycles (0.854ms to 1.22ms). Failure to ensure this timing causes the event to be ignored. Thus, it is
recommended that you design with the maximum timing specs. See Figure 5.

INT has a weak internal pulldown resistor to prevent the pin from floating if the signal connected to the
pin is tri-stated. Without the resistor, the input would float and potentially log phantom events. With the
pulldown resistor, the pin can be transitioned to a low state, causing an event to be recorded if INT is held
high by an outside signal that becomes tri-stated.

Figure 5. Event Recognition Timing

                    EVENT ON RISING EDGE                                EVENT ON BOTH EDGES

GOOD EVENTS                                            GOOD EVENTS

         t GLITCH               tEVENT                          tGLITCH                       tEVENT

INT                                        TRANSITION  INT                                         TRANSITION
                                           POINT                                                   POINT

                       EVENT 1  EVENT 2                                      EVENT 1 EVENT 2
                                                       BAD EVENT 1
BAD EVENT 1
                                           TRANSITION           t GLITCH                      TRANSITION
             t GLITCH                      POINT                                              POINT
                                                       INT
    INT

BAD EVENT 2                                            BAD EVENT 2
    INT
                                tEVENT                                                        tEVENT
                       EVENT 1
                                           TRANSITION  INT                                    TRANSITION
                                           POINT
                                                                                              POINT

                                 EVENT 2                                  EVENT 1 EVENT 2
                                IS MISSED
                                                                          IS MISSED

                                           21 of 25
                                                                                                              DS1678 Real-Time Event Recorder

SECURITY

The DS1678 provides several measures to ensure data integrity for the end user. These security measures
are intended to prevent third-party intermediaries from tampering with the data that has been stored in the
event-log memory.

As a first security measure, the event-log memory is read-only from the perspective of the end user. The
DS1678 can write the data into these memory banks, but the end user cannot write data to individual
registers. This prevents an unscrupulous intermediary from writing false data to the DS1678. The end
user, however, can clear the contents of the event-log memory. A new mission cannot be started unless
the MEM CLR bit has been set to one to indicate that the memory and registers are cleared.

As a second security measure, changing any value in the memory including the RTC and control registers
stops event logging and clears the MIP and ME bits. The MEM CLR bit must be set to one so the
memory and registers are cleared before a new event-log mission can begin.

I2C SERIAL DATA BUS

The DS1678 supports a bidirectional I2C bus and data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, and a device receiving data as a receiver. The device that controls
the message is called a "master." The devices that are controlled by the master are "slaves." The bus must
be controlled by a master device that generates the serial clock (SCL), controls the bus access, and
generates the START and STOP conditions. The DS1678 operates as a slave on the I2C bus. Connections
to the bus are made via the open-drain I/O lines SDA and SCL.

The following bus protocol has been defined (Figure 6):
    Data transfer can be initiated only when the bus is not busy.
    During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in
    the data line while the clock line is HIGH are interpreted as control signals.

Accordingly, the following bus conditions have been defined:

Bus not busy: Both data and clock lines remain HIGH.

Start data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is HIGH,
defines a START condition.

Stop data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is
HIGH, defines the STOP condition.

Data valid: The state of the data line represents valid data when, after a START condition, the data line
is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed
during the LOW period of the clock signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a START condition and terminated with a STOP condition. The
number of data bytes transferred between START and STOP conditions is not limited, and is determined
by the master device. The information is transferred byte-wise and each receiver acknowledges with a
ninth bit. Within the bus specifications a standard mode (100kHz clock rate) and a fast mode (400kHz
clock rate) are defined. The DS1678 works in both modes.

Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the
reception of each byte. The master device must generate an extra clock pulse which is associated with this
acknowledge bit.

                                                                        22 of 25
                                                                                                              DS1678 Real-Time Event Recorder

A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse. Of
course, setup and hold times must be taken into account. A master must signal an end of data to the slave
by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the master to generate the STOP condition.
Figure 6 details how data transfer is accomplished on the I2C bus. Depending upon the state of the R/W
bit, two types of data transfer are possible:

1) Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the
    master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge
    bit after each received byte.

2) Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is
    transmitted by the master. The slave then returns an acknowledge bit. Next follows a number of data
    bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received
    bytes other than the last byte. At the end of the last received byte, a "not acknowledge" is returned.

The master device generates all the serial clock pulses and the START and STOP conditions. A transfer is
ended with a STOP condition or with a repeated START condition. Because a repeated START condition
is also the beginning of the next serial transfer, the bus is not released.

The DS1678 can operate in the following two modes:

1) Slave receiver mode (DS1678 write mode): Serial data and clock are received through SDA and
    SCL. After each byte is received, the receiver transmits an acknowledge bit. START and STOP
    conditions are recognized as the beginning and end of a serial transfer. The slave address byte is the
    first byte received after master generates the START condition. The address byte contains the 7-bit
    DS1678 address, which is 1001010, followed by the direction bit (R/W), which is 0. The second byte
    from the master is the register address. This sets the register pointer. If the write is being done to set
    the register pointer, a STOP or repeated START may then be sent by the master. Otherwise, the
    master then transmits each byte of data, with the DS1678 acknowledging each byte received. The
    master generates a STOP condition to terminate the data write (Figure 7).

2) Slave transmitter mode (DS1678 read mode): The first byte is received and handled as in the slave
    receiver mode. However, in this mode, the direction bit indicates that the transfer direction is
    reversed. Serial data is transmitted on SDA by the DS1678 while the serial clock is input on SCL. The
    slave address byte is the first byte received after the master generates a START condition. The
    address byte contains the 7-bit DS1678 address, which is 1001010, followed by the direction bit
    (R/W), which is 1. After receiving a valid slave address byte and direction bit, the DS1678 generates
    an acknowledge on the SDA line. The DS1678 begins to transmit data on each SCL pulse starting
    with the register address pointed to by the register pointer. As the master reads each byte, it must
    generate an acknowledge. The DS1678 must receive a "not acknowledge" on the last byte to end a
    read (Figure 7).

                                                                        23 of 25
                                                                                                                         DS1678 Real-Time Event Recorder

Figure 6. Data Transfer on I2C Serial Bus

SDA                          MSB         slave address
                                   1
SCL                                                                         R/W                                                          acknowledgement
                      START                                               direction                                                      signal from receiver

                  CONDITION                                                   bit

                                                                                     acknowledgement
                                                                                     signal from receiver

                                      2                   6  7            8          9                     1  2  3-8                     8    9
                                                                                                                                            ACK
                                                                                     ACK

                                                                                                                 repeated if more bytes                        STOP CONDITION
                                                                                                                      are transferred                                       OR

                                                                                                                                                                     REPEATED
                                                                                                                                                               START CONDITION

Figure 7. I2C Serial Communication with DS1678

     W rite to Mem ory Address Pointer

SCL

SDA  S 1 0 0 1 0 1 0 W A A7 A6 A5 A4 A3 A2 A1 A0 A P

     S ta rt                 Device Address Byte  DS1678     Mem ory Address Byte         DS1678 Stop
                                                   ACK                                     ACK

     W rite to Mem ory Location (Single Byte)

SCL

SDA  S 1 0 0 1 0 1 0 W A A7 A6 A5 A4 A3 A2 A1 A0 A D7 D6 D5 D4 D3 D2 D1 D0 A P

     Start                   Device Address Byte  DS1678 M em ory Address Byte            DS1678              Data Byte                     DS1678 Stop
                                                   ACK                                     ACK                                               ACK

     Read Single Byte from Current M em ory Address Pointer Location

SCL

SDA  S 1 0 0 1 0 1 0 Rd A D7 D6 D5 D4 D3 D2 D1 D0 N                                                        P

     Start                   Device Address Byte  DS1678        Data Byte                 Master Stop
                                                   ACK                                    NACK

     Read M ultiple Bytes from Current M em ory Address Pointer Location

SCL

SDA  S 1 0 0 1 0 1 0 Rd A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 N                                                                    P

     Start                   Device Address Byte  DS1678     M ost Significant            M as ter            Least Significant             Master Stop
                                                   ACK           Data Byte                 ACK                     Data Byte                NACK

     Read Single Byte from New M em ory Address Pointer Location

SCL

SDA  S 1 0 0 1 0 1 0 W A A7 A6 A5 A4 A3 A2 A1 A0 A                                                         R 1 0 0 1 0 1 0 Rd A

     Start                   Device Address Byte  DS1678 Mem ory Address Byte             DS1678 Repeated        Device Address             DS1678
      SCL                                          ACK                                     ACK Start                      B yte              ACK
     SDA
                             D7 D6 D5 D4 D3 D2 D1 D0 N          P

                                      Data Byte              Master Stop
                                                             NACK

                                                                          24 of 25
                                       DS1678 Real-Time Event Recorder

CHIP INFORMATION

TRANSISTOR COUNT: 110,836
PROCESS: CMOS
SUBSTRATE CONNECTED TO GROUND

THERMAL INFORMATION

PART    THETA-JA     THETA-JC
          (C/W)       (C/W)

8 PDIP  110          40

8 SO    113          31

PACKAGE INFORMATION

(For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.)

    PACKAGE            DOCUMENT
                         NUMBER
8-Pin Plastic DIP
     (300 mils)      56-G5005-000.pdf

8-Pin SO (208 mils)  56-G4010-001.pdf

                                                                        25 of 25

Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.
No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
                                                                2005 Maxim Integrated Products Printed USA

     The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.
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