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Ultrafast SiGe
Voltage Comparators
ADCMP580/ADCMP581/ADCMP582
FEATURES
180 ps propagation delay
25 ps overdrive and slew rate dispersion
8 GHz equivalent input rise time bandwidth
100 ps minimum pulse width
37 ps typical output rise/fall
10 ps deterministic jitter (DJ)
200 fs random jitter (RJ)
−2 V to +3 V input range with +5 V/−5 V supplies
On-chip terminations at both input pins
Resistor-programmable hysteresis
Differential latch control
Power supply rejection > 70 dB
FUNCTIONAL BLOCK DIAGRAM
V
CCI
V
TP
TERMINATION
V
P
NONINVERTING
INPUT
V
CCO
V
N
INVERTING
INPUT
V
TN
TERMINATION
ADCMP580/
ADCMP581/
ADCMP582
Q OUTPUT
CML/ECL/
PECL
Q OUTPUT
V
EE
LE INPUT
04672-001
HYS
V
EE
LE INPUT
APPLICATIONS
Automatic test equipment (ATE)
High speed instrumentation
Pulse spectroscopy
Medical imaging and diagnostics
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
Clock and data signal restoration
Figure 1.
GENERAL DESCRIPTION
The ADCMP580/ADCMP581/ADCMP582 are ultrafast voltage
comparators fabricated on the Analog Devices, Inc. proprietary
XFCB3 Silicon Germanium (SiGe) bipolar process. The
ADCMP580 features CML output drivers, the ADCMP581
features reduced swing ECL (negative ECL) output drivers, and
the ADCMP582 features reduced swing PECL (positive ECL)
output drivers.
All three comparators offer 180 ps propagation delay and 100 ps
minimum pulse width for 10 Gbps operation with 200 fs random
jitter (RJ). Overdrive and slew rate dispersion are typically less
than 15 ps.
The ±5 V power supplies enable a wide −2 V to +3 V input
range with logic levels referenced to the CML/NECL/PECL
outputs. The inputs have 50 Ω on-chip termination resistors
with the optional capability to be left open (on an individual
pin basis) for applications requiring high impedance input.
The CML output stage is designed to directly drive 400 mV into
50 Ω transmission lines terminated to ground. The NECL output
stages are designed to directly drive 400 mV into 50 Ω terminated
to −2 V. The PECL output stages are designed to directly drive
400 mV into 50 Ω terminated to V
CCO
− 2 V. High speed latch
and programmable hysteresis are also provided. The differential
latch input controls are also 50 Ω terminated to an independent
V
TT
pin to interface to either CML or ECL or to PECL logic.
The ADCMP580/ADCMP581/ADCMP582 are available in a
16-lead LFCSP_VQ.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2005–2007 Analog Devices, Inc. All rights reserved.
ADCMP580/ADCMP581/ADCMP582
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Information ......................................................................... 5
Absolute Maximum Ratings............................................................ 6
Thermal Considerations.............................................................. 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 8
Typical Application Circuits ......................................................... 10
Application Information................................................................ 11
Power/Ground Layout and Bypassing..................................... 11
ADCMP58x Family of Output Stages ..................................... 11
Using/Disabling the Latch Feature........................................... 11
Optimizing High Speed Performance ..................................... 12
Comparator Propagation Delay Dispersion............................... 12
Comparator Hysteresis .............................................................. 13
Minimum Input Slew Rate Requirement ................................ 13
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 14
REVISION HISTORY
8/07—Rev. 0 to Rev. A
Changes to Figure 1.......................................................................... 1
Changes to Table 4............................................................................ 7
Changes to Figure 9.......................................................................... 8
Changes to Figure 21, Figure 22, and Figure 23 ......................... 10
Changes to Using/Disabling the Latch Feature .......................... 11
Changes to Comparator Hysteresis Section and Figure 29....... 13
Changes to Ordering Guide .......................................................... 14
7/05—Revision 0: Initial Version
Rev. A | Page 2 of 16
ADCMP580/ADCMP581/ADCMP582
SPECIFICATIONS
V
CCI
= 5.0 V; V
EE
= −5.0 V; V
CCO
= 3.3 V; T
A
= 25°C, unless otherwise noted.
Table 1.
Parameter
DC INPUT CHARACTERISTICS
Input Voltage Range
Input Differential Range
Input Offset Voltage
Offset Voltage Temperature Coefficient
Input Bias Current
Input Bias Current Temperature Coefficient
Input Offset Current
Input Resistance
Input Resistance, Differential Mode
Input Resistance, Common Mode
Active Gain
Common-Mode Rejection Ratio
Hysteresis
LATCH ENABLE CHARACTERISTICS
Latch Enable Input Impedance
Latch-to-Output Delay
Latch Minimum Pulse Width
ADCMP580 (CML)
Latch Enable Input Range
Latch Enable Input Differential
Latch Setup Time
Latch Hold Time
ADCMP581 (NECL)
Latch Enable Input Range
Latch Enable Input Differential
Latch Setup Time
Latch Hold Time
ADCMP582 (PECL)
Latch Enable Input Range
Latch Enable Input Differential
Latch Setup Time
Latch Hold Time
DC OUTPUT CHARACTERISTICS
ADCMP580 (CML)
Output Impedance
Output Voltage High Level
Output Voltage Low Level
Output Voltage Differential
ADCMP581 (NECL)
Output Voltage High Level
Output Voltage High Level
Output Voltage High Level
Output Voltage Low Level
Output Voltage Low Level
Output Voltage Low Level
Output Voltage Differential
Symbol
V
P
, V
N
V
OS
ΔV
OS
/d
T
I
P
, I
N
ΔI
B
/d
T
Condition
Min
−2.0
−2.0
−10.0
Open termination
Typ
Max
+3.0
+2.0
+10.0
30.0
±5.0
Unit
V
V
mV
μV/°C
μA
nA/°C
μA
Ω
kΩ
kΩ
dB
dB
mV
Ω
ps
ps
0
0.5
V
V
ps
ps
V
V
ps
ps
V
V
ps
ps
Open termination
Open termination
A
V
CMRR
V
CM
= −2.0 V to +3.0 V
R
HYS
= ∞
Each pin, V
TT
at ac ground
V
OD
= 200 mV
V
OD
= 200 mV
−0.8
0.2
t
S
t
H
V
OD
= 200 mV
V
OD
= 200 mV
−1.8
0.2
t
S
t
H
V
OD
= 200 mV
V
OD
= 200 mV
V
CCO
− 1.8
0.2
t
S
t
H
V
OD
= 200 mV
V
OD
= 200 mV
±4
10
15
50
+2
47 to 53
50
500
48
60
1
47 to 53
175
100
Z
IN
t
PLOH
, t
PLOL
t
PL
0.4
95
−90
0.4
70
−65
+0.8
0.5
0.4
30
−25
V
CCO
− 0.8
0.5
Z
OUT
V
OH
V
OL
50 Ω to GND
50 Ω to GND
50 Ω to GND
50 Ω to −2 V, T
A
= 125°C
50 Ω to −2 V, T
A
= 25°C
50 Ω to −2 V, T
A
= −55°C
50 Ω to −2 V, T
A
= 125°C
50 Ω to −2 V, T
A
= 25°C
50 Ω to −2 V, T
A
= −55°C
50 Ω to −2.0 V
−0.10
−0.50
340
−0.99
−1.06
−1.11
−1.43
−1.50
−1.55
340
50
0
−0.40
395
−0.87
−0.94
−0.99
−1.26
−1.33
−1.38
395
+0.03
−0.35
450
−0.75
−0.82
−0.87
−1.13
−1.20
−1.25
450
Ω
V
V
mV
V
V
V
V
V
V
mV
V
OH
V
OH
V
OH
V
OL
V
OL
V
OL
Rev. A | Page 3 of 16
ADCMP580/ADCMP581/ADCMP582
Parameter
ADCMP582 (PECL)
Output Voltage High Level
Output Voltage High Level
Output Voltage High Level
Output Voltage Low Level
Output Voltage Low Level
Output Voltage Low Level
Output Voltage Differential
AC PERFORMANCE
Propagation Delay
Propagation Delay Temperature Coefficient
Propagation Delay Skew—Rising
Transition to Falling Transition
Overdrive Dispersion
Slew Rate Dispersion
Pulse Width Dispersion
Duty Cycle Dispersion 5% to 95%
Common-Mode Dispersion
Equivalent Input Bandwidth
1
Toggle Rate
Deterministic Jitter
Deterministic Jitter
RMS Random Jitter
Minimum Pulse Width
Minimum Pulse Width
Rise/Fall Time
POWER SUPPLY
Positive Supply Voltage
Negative Supply Voltage
ADCMP580 (CML)
Positive Supply Current
Negative Supply Current
Power Dissipation
ADCMP581 (NECL)
Positive Supply Current
Negative Supply Current
Power Dissipation
ADCMP582 (PECL)
Logic Supply Voltage
Input Supply Current
Output Supply Current
Negative Supply Current
Power Dissipation
Power Supply Rejection (V
CCI
)
Power Supply Rejection (V
EE
)
Power Supply Rejection (V
CCO
)
1
Symbol
V
OH
V
OH
V
OH
V
OL
V
OL
V
OL
Condition
V
CCO
= 3.3 V
50 Ω to V
CCO
− 2 V, T
A
= 125°C
50 Ω to V
CCO
− 2 V, T
A
= 25°C
50 Ω to V
CCO
− 2 V, T
A
= −55°C
50 Ω to V
CCO
− 2 V, T
A
= 125°C
50 Ω to V
CCO
− 2 V, T
A
= 25°C
50 Ω to V
CCO
− 2 V, T
A
= −55°C
50 Ω to V
CCO
− 2.0 V
V
OD
= 500 mV
V
OD
= 500 mV, 5 V/ns
50 mV < V
OD
< 1.0 V
10 mV < V
OD
< 200 mV
2 V/ns to 10 V/ns
100 ps to 5 ns
1.0 V/ns, 15 MHz, V
CM
= 0.0 V
V
OD
= 0.2 V, −2 V < V
CM
< 3 V
0.0 V to 400 mV input,
t
R
= t
F
= 25 ps, 20/80
>50% output swing
V
OD
= 500 mV, 5 V/ns,
PRBS
31
− 1 NRZ, 5 Gbps
V
OD
= 200 mV, 5 V/ns,
PRBS
31
− 1 NRZ, 10 Gbps
V
OD
= 200 mV, 5 V/ns, 1.25 GHz
Δt
PD
< 5 ps
Δt
PD
< 10 ps
20/80
Min
V
CCO
− 0.99
V
CCO
− 1.06
V
CCO
− 1.11
V
CCO
− 1.43
V
CCO
− 1.50
V
CCO
− 1.55
340
Typ
V
CCO
− 0.87
V
CCO
− 0.94
V
CCO
− 0.99
V
CCO
− 1.26
V
CCO
− 1.33
V
CCO
− 1.35
395
180
0.25
10
10
15
15
15
10
5
8
12.5
15
25
0.2
100
80
37
Max
V
CCO
− 0.75
V
CCO
− 0.82
V
CCO
− 0.87
V
CCO
− 1.13
V
CCO
− 1.20
V
CCO
− 1.25
450
Unit
V
V
V
V
V
V
mV
ps
ps/°C
ps
ps
ps
ps
ps
ps
ps/V
GHz
Gbps
ps
ps
ps
ps
ps
ps
t
PD
Δt
PD
/d
T
BW
EQ
DJ
DJ
RJ
PW
MIN
PW
MIN
t
R,
t
F
V
CCI
V
EE
I
VCCI
I
VEE
P
D
I
VCCI
I
VEE
P
D
V
CCO
I
VCCI
I
VCCO
I
VEE
P
D
PSR
VCCI
PSR
VEE
PSR
VCCO
+4.5
−5.5
V
CCI
= 5.0 V, 50 Ω to GND
V
EE
= −5.0 V, 50 Ω to GND
50 Ω to GND
V
CCI
= 5.0 V, 50 Ω to −2 V
V
EE
= −5.0 V, 50 Ω to −2 V
50 Ω to −2 V
+5.0
−5.0
6
−40
230
6
−25
155
+3.3
6
44
−25
310
−75
−60
−75
+5.5
−4.5
8
−34
260
8
−19
200
+5.0
8
55
−19
350
V
V
mA
mA
mW
mA
mA
mW
V
mA
mA
mA
mW
dB
dB
dB
−50
−35
+2.5
V
CCI
= 5.0 V, 50 Ω to V
CCO
− 2 V
V
CCO
= 5.0 V, 50 Ω to V
CCO
− 2 V
V
EE
= −5.0 V, 50 Ω to V
CCO
− 2 V
50 Ω to V
CCO
− 2 V
V
CCI
= 5.0 V + 5%
V
EE
= −5.0 V + 5%
V
CCO
= 3.3 V + 5% (ADCMP582)
−35
Equivalent input bandwidth assumes a simple first-order input response and is calculated with the following formula:
BW
EQ
= 0.22/(tr
COMP
2
–
tr
IN
2
), where
tr
IN
is the 20/80
transition time of a quasi-Gaussian input edge applied to the comparator input and
tr
COMP
is the effective transition time digitized by the comparator.
Rev. A | Page 4 of 16
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