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AD5933

器件型号:AD5933
厂商名称:ADI [Analog Devices Inc]
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器件描述

1 MSPS 12-Bit Impedance Converter, Network Analyzer

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Preliminary Technical Data
FEATURES
50KHz Max Excitation Output
Impedance Range .1k-20M, 12 Bit Resolution
Selectable System Clock from the following:
PLL, RC Oscillator, External Clock
DSP Real and Imaginary Calculation (FFT)
3V Power Supply,
Programmable Sinewave Output
Frequency Resolution 27 Bits (<0.1Hz)
Frequency Sweep Capability
12 Bit Sampling ADC
ADC Sampling 1MSPS, INL +/- 1LSB Max.
On Chip Temp Sensor allows +/-2 oC accuracy
Serial
I2
C Loading
Temperature Range –40-125oC 16 SSOP
1 MSPS 12-Bit Impedance Converter,
Network Analyzer
AD5933
To determine the actual real impedance value Z(W) , generally a
frequency sweep is performed. The impedance can be
calculated at each point and a frequency vs magnitude plot can
be created.
The system allows the user to program a 2V PK-PK sinusoidal
signal as excitation to an external load. Output ranges of 1V,
500mV, 200mV can also be programmed. The signal is
provided on chip using DDS techniques. Frequency resolution
of 27 bits (less than 0.1HZ) can be achieved. The clock for the
DDS can be generated from an external reference clock, an
internal RC oscillator or an internal PLL. The PLL has a gain
stage of 512 and typically needs a reference clock of 32KHz on
the MCLK pin.
To perform the frequency sweep, the user must first program
the conditions required for the sweep; start frequency, delta
frequency, step frequency, etc. A Start Command is then
required to begin the sweep.
At each point on the sweep the ADC will take 1024 samples and
calculate a Discrete Fourier Transform to provide the real and
imaginary data for the waveform. The real and imaginary data
is available to the user through the 12C interface.
To determine the impedance of the load at any one frequency
point, Z(w), a measurement system comprised of a trans
impedance amplifier, gain stage and ADC are used to record
data. The gain stage for the response stage is 1 or 5.
The ADC is a low noise, high speed 1MSPS sampling ADC that
operates from a 3V supply. Clocking for both the DDS and
ADC signals is provided externally via the MCLK reference
clock, which is provided externally from a crystal oscillator. The
AD5933 is available in a 16 ld SSOP.
APPLICATIONS
Complex Impedance Measurement
Impedance Spectrometry
Biomedical and Automotive Sensors
Proximity Sensors
FFT Processing
GENERAL DESCRIPTION
The AD5933 is a high precision impedance converter system
solution which combines an on board frequency generator with
a 12 Bit 1MSPS ADC. The frequency generator allows an
external complex impedance to be excited with a known
frequency. The response signal from the impedance is sampled
by the on board ADC and FFT processed by an on-board DSP
engine. The FFT algorithm returns a Real (R) and Imaginary (I)
data word, allowing impedance to be conveniently calculated.
The impedance magnitude and phase is easily calculated using
the following equations:
Magnitude =
-1
R + I
2
2
Phase = Tan (I/R)
MCLK
G=1/0.5/0.2/0.1
PLL
DDS CORE
(27 Bits)
VOUT = 2V (G=1)
DAC
÷4
RC Osc
÷4
Rfb
Z(w)
Digital Control
Logic
G=1/5
1024 POINT DFT
REAL DATA 16Bits
ADC
(12Bit)
VB
IMAGE DATA 16Bits
I2C Interface
INTERNAL
BANDGAP
REFERENCE
TEMP
SENSOR
SCL
SDA
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
AD5933
TABLE OF CONTENTS
Specifications..................................................................................... 3
Timing Characteristics..................................................................... 5
Pin Configuration and function description ................................ 6
General Description ......................................................................... 7
Output Stage.................................................................................. 7
Circuit Description....................................................................... 7
Numerical Controlled Oscillator + Phase Modulator ............. 7
SIN ROM ....................................................................................... 8
Response Stage.............................................................................. 8
ADC Operation ............................................................................ 8
DFT Conversion ........................................................................... 8
Temperature Sensor ..................................................................... 9
Register Map (Each Row equals 8 Bits of Data) ......................... 11
Control Register.......................................................................... 13
Control Register Decode: .......................................................... 14
Initialize Sensor with Start Frequency..................................... 14
Start Frequency Sweep............................................................... 14
Increment Frequency ................................................................. 14
Repeat Frequency ....................................................................... 14
Power Down................................................................................ 14
Preliminary Technical Data
Standby Mode ............................................................................. 14
Read Temperature ...................................................................... 14
Error Checking ........................................................................... 14
RESET .......................................................................................... 14
System Clock............................................................................... 14
Output Voltage............................................................................ 14
Post Gain ..................................................................................... 14
Performing a Frequency Sweep – Flow Chart ............................ 15
Serial Bus Interface..................................................................... 15
General I
2
C Timing.................................................................... 15
Writing/Reading to the AD5933 .............................................. 16
Block Write.................................................................................. 17
AD5933 Read Operations ......................................................... 17
Error Correction......................................................................... 18
P.E.C. ............................................................................................ 18
Checksum.................................................................................... 18
User Command Codes .............................................................. 18
Outline Dimensions ....................................................................... 20
ESD Caution................................................................................ 20
REVISION HISTORY
12/04—Revision PrA—Preliminary Version
Rev. PrA | Page 2 of 20
Preliminary Technical Data
SPECIFICATIONS
V
DD
= +3.0 V +/- 10%, T
MIN
to T
MAX
unless otherwise noted.
Table 1.
Parameter
System Specs:
Impedance Range
Total System Accuracy
System ppm
MCLK Update Rate
Output Stage
Frequency Specs
Output Frequency Range
Frequency Resoltuion
MCLK
Initial Frequency Accuracy
RC OSCILLATOR
Initial Frequency Accuracy
Calibrated Frequency Accuracy
Frequency Tempco
Frequency Jitter
PLL
PLL Gain
INPUT CLOCK RANGE
Frequency Jitter
Output Voltage Specs
AC Voltage Range
Output Voltage Error
DC Bias
DC Bias Error
AC Voltage Range
Output Voltage Error
DC Bias
DC Bias Error
AC Voltage Range
Output Voltage Error
DC Bias
DC Bias Error
AC Voltage Range
Output Voltage Error
DC Bias
DC Bias Error
DC Output Impedance
Short Circuit Current
Short Circuit Current
AC Characteristics
Signal to Noise Ratio
Total Harmonic Distortion
Spurious free Dynamic Range
Wideband
B Version
1
Min Typ Max
.0001
1
TDB
16
20
Unit
Test Conditions/Comments
AD5933
M Ohm
%
ppm/oC
MSPS
0
27
0.1
50KHz
Hz
Bits.
Hz
Uni-Polar Sinusoidal Signal.
<0.1 Hz Resolution
External Rerference Clock. Typically 16.667MHz.
Output Exitation Accuracy. 0 -50KHz Range.
Internal RC Oscillator.
Output Excitation Accuracy. 0 -50KHz Range.
0 -50KHz Range.
1 point Offset Calibration
Requires 2 point User Calibration.
Jitter on VOUT Pin, 30KHz output.
1.5
0.1
10
TDB
512
32
TDB
2.0
TBD
Vdd/2
TBD
1.0
TBD
Vdd/4
±1
0.4
TBD
Vdd/8
TBD
0.2
TBD
Vdd/16
TBD
120
75
100
60
-66
60
%
Hz
ppm/oC
KHZ
Jitter on VOUT Pin, 30KHz output.
Volts
%
Volts
%
Volts
%
Volts
%
Volts
%
Volts
%
Volts
%
Volts
%
Ohm
mA
mA
db
db
db
Rev. PrA | Page 3 of 20
Pk-Pk Unipolar Voltage on Output.
Voltage Error on Pk-Pk Output.
DC bias of AC Signal
Tolerance of DC Bias
Pk-Pk Unipolar Voltage on Output.
Voltage Error on Pk-Pk Output.
DC bias of AC Signal
Tolerance of DC Bias
Pk-Pk Unipolar Voltage on Output.
Voltage Error on Pk-Pk Output.
DC bias of AC Signal
Tolerance of DC Bias
Pk-Pk Unipolar Voltage on Output.
Voltage Error on Pk-Pk Output.
DC bias of AC Signal
Tolerance of DC Bias
At 3 Volts.
At 5 Volts.
AD5933
Parameter
Narrowband
Clock Feedthrough
System Response Stage
Analog Input VIN
Input Leakage Current
Input Capacitance
Input Impedance
ADC Accuracy
Resolution
Sampling Rate
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
TEMPERATURE SENSOR
Accuracy
Resolution
Temperature Conversion Time
LOGIC INPUTS
Vih, Input High Voltage
Vil, Input Low Voltage
Input Current
Input Capacitance
POWER REQUIREMENTS
Vdd
IDD (Normal Mode)
IDD (Powerdown Mode)
B Version
1
Min Typ Max
80
TBD
Unit
db
db
Preliminary Technical Data
Test Conditions/Comments
1
0.5
100M
12
1
±1
±1
nA
pF
Ohm
To Pin VIN
To Pin VIN
To Pin VIN
MSPS
LSB
LSB
No missing Codes
±1
0.03125
TBD
2.2
0.8
±1
±3
3.0
15
TBD
oC
oC
uS
VDD = 3v
VDD = 3V
uA
pF
Volts
mA
uA
TA = -40 - 125 DEGREES
1
2
Temperature ranges are as follows: B Version: –40°C to +125°C, typical at 25°C.
Guaranteed by design and characterization, not production tested.
Rev. PrA | Page 4 of 20
Preliminary Technical Data
TIMING CHARACTERISTICS
Table 2. I
2
C Serial Interface
Parameter
1
F
SCL
t
1
t
2
t
3
t
4
t
5
t
62
t
7
t
8
t
9
t
10
t
11
Limit at T
MIN
, T
MAX
400
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
300
0
300
0
300
20 + 0.1 C
B
400
Unit
kHz max
µs min
µs min
µs min
µs min
ns min
µs max
µs min
µs min
µs min
µs min
ns max
ns min
ns max
ns min
ns max
ns min
pF max
Description
SCL clock frequency
SCL cycle time
t
HIGH
, SCL high time
t
LOW
, SCL low time
t
HD
,
STA
, start/repeated start condition hold time
t
SU
,
DAT
, data setup time
t
HD
,
DAT
data hold time
t
HD
,
DAT
data hold time
t
SU
,
STA
setup time for repeated start
t
SU
,
STO
stop condition setup time
t
BUF
, bus free time between a stop and a start condition
t
F
, fall time of SDA when transmitting
t
R
, rise time of SCL and SDA when receiving (CMOS compatible)
t
F
, fall time of SDA when transmitting
t
F
, fall time of SDA when receiving (CMOS compatible)
t
F
, fall time of SCL and SDA when receiving
t
F
, fall time of SCL and SDA when transmitting
Capacitive load for each bus line
AD5933
C
B3
SDA
t
9
t
3
t
10
t
11
t
4
SCL
t
4
START
CONDITION
t
6
t
2
t
5
t
7
REPEATED
START
CONDITION
t
1
t
8
STOP
CONDITION
03773-0-007
Figure 1. I
2
C Interface Timing Diagram
Rev. PrA | Page 5 of 20

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