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5SGSED6N2F45I3N

器件型号:5SGSED6N2F45I3N
器件类别:半导体    可编程逻辑器件   
文件大小:8444.62KB,共10页
厂商名称:Altera (Intel)
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器件描述

FPGA - Field Programmable Gate Array FPGA - Stratix V GS 2320 LABS 840 IOs

参数
参数名称属性值
Manufacturer:Intel
RoHS:Details
Product:Stratix V GS
Number of Logic Elements:583000
Number of Logic Array Blocks - LABs:220000
Number of I/Os:840 I/O
Operating Supply Voltage:850 mV
Minimum Operating Temperature:- 40 C
Maximum Operating Temperature:+ 85 C
Mounting Style:SMD/SMT
Package / Case:FBGA-1932
Packaging:Tray
Brand:Intel / Altera
Data Rate:14.1 Gb/s
Embedded Block RAM - EBR:6.71 Mbit
Number of Transceivers:48 Transceiver
Series:Stratix V GS 5SGSD6
Factory Pack Quantity:12
Total Memory:51.71 Mbit
Tradename:Stratix V FPGA

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2015.10.01
Stratix V Device Overview
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SV51001
Altera’s 28-nm Stratix
®
V FPGAs include innovations such as an enhanced core architecture, integrated
transceivers up to 28.05 gigabits per second (Gbps), and a unique array of integrated hard intellectual
property (IP) blocks.
With these innovations, Stratix V FPGAs deliver a new class of application-targeted devices optimized for:
• Bandwidth-centric applications and protocols, including PCI Express
®
(PCIe
®
) Gen3
• Data-intensive applications for 40G/100G and beyond
• High-performance, high-precision digital signal processing (DSP) applications
Stratix V devices are available in four variants (GT, GX, GS, and E), each targeted for a different set of
applications. For higher volume production, you can prototype with Stratix V FPGAs and use the low-
risk, low-cost path to HardCopy
®
V ASICs.
Related Information
Stratix V Device Handbook: Known Issues
Lists the planned updates to the
Stratix V Device Handbook
chapters.
Stratix V Family Variants
The Stratix V device family contains the GT, GX, GS, and E variants.
Stratix V GT
devices, with both 28.05-Gbps and 12.5-Gbps transceivers, are optimized for applications
that require ultra-high bandwidth and performance in areas such as 40G/100G/400G optical communica‐
tions systems and optical test systems. 28.05-Gbps and 12.5-Gbps transceivers are also known as GT and
GX channels, respectively.
Stratix V GX
devices offer up to 66 integrated transceivers with 14.1-Gbps data rate capability. These
transceivers also support backplane and optical interface applications. These devices are optimized for
high-performance, high-bandwidth applications such as 40G/100G optical transport, packet processing,
and traffic management found in wireline, military communications, and network test equipment
markets.
Stratix V GS
devices have an abundance of variable precision DSP blocks, supporting up to 3,926 18x18
or 1,963 27x27 multipliers. In addition, Stratix V GS devices offer integrated transceivers with 14.1-Gbps
data rate capability. These transceivers also support backplane and optical interface applications. These
devices are optimized for transceiver-based DSP-centric applications found in wireline, military,
broadcast, and high-performance computing markets.
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at
www.altera.com/common/legal.html.
Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
©
ISO
9001:2008
Registered
www.altera.com
101 Innovation Drive, San Jose, CA 95134
2
Stratix V Features Summary
SV51001
2015.10.01
Stratix V E
devices offer the highest logic density within the Stratix V family with nearly one million logic
elements (LEs) in the largest device. These devices are optimized for applications such as ASIC and system
emulation, diagnostic imaging, and instrumentation.
Common to all Stratix V family variants are a rich set of high-performance building blocks, including a
redesigned adaptive logic module (ALM), 20 Kbit (M20K) embedded memory blocks, variable precision
DSP blocks, and fractional phase-locked loops (PLLs). All of these building blocks are interconnected by
Altera’s superior multi-track routing architecture and comprehensive fabric clocking network.
Also common to Stratix V devices is the new Embedded HardCopy Block, which is a customizable hard
IP block that leverages Altera’s unique HardCopy ASIC capabilities. The Embedded HardCopy Block in
Stratix V FPGAs is used to harden IP instantiation of PCIe Gen3, Gen2, and Gen1.
Stratix V Features Summary
Table 1: Summary of Features for Stratix V Devices
Feature
Description
Technology
Low-power serial
transceivers
• 28-nm TSMC process technology
• 0.85-V or 0.9-V core voltage
• 28.05-Gbps transceivers on Stratix V GT devices
• Electronic dispersion compensation (EDC) for XFP, SFP+, QSFP, CFP
optical module support
• Adaptive linear and decision feedback equalization
• Transmitter pre-emphasis and de-emphasis
• Dynamic reconfiguration of individual channels
• On-chip instrumentation (EyeQ non-intrusive data eye monitoring)
• 600-Megabits per second (Mbps) to 12.5-Gbps data rate capability
1.6-Gbps LVDS
1,066-MHz external memory interface
On-chip termination (OCT)
1.2-V to 3.3-V interfacing for all Stratix V devices
Backplane capability
General-purpose I/Os
(GPIOs)
Embedded HardCopy
Block
Embedded transceiver
hard IP
• PCIe Gen3, Gen2, and Gen1 complete protocol stack, x1/x2/x4/x8 end
point and root port
Interlaken physical coding sublayer (PCS)
Gigabit Ethernet (GbE) and XAUI PCS
10G Ethernet PCS
Serial RapidIO
®
(SRIO) PCS
Common Public Radio Interface (CPRI) PCS
Gigabit Passive Optical Networking (GPON) PCS
Power management
• Programmable Power Technology
• Quartus II integrated PowerPlay Power Analysis
Altera Corporation
Stratix V Device Overview
Send Feedback
SV51001
2015.10.01
Stratix V Family Plan
3
Feature
Description
High-performance core
fabric
Embedded memory
blocks
Variable precision DSP
blocks
• Enhanced ALM with four registers
• Improved routing architecture reduces congestion and improves compile
times
• M20K: 20-Kbit with hard error correction code (ECC)
• MLAB: 640-bit
• Up to 600 MHz performance
• Natively support signal processing with precision ranging from 9x9 up to
54x54
• New native 27x27 multiply mode
• 64-bit accumulator and cascade for systolic finite impulse responses (FIRs)
• Embedded internal coefficient memory
• Pre-adder/subtractor improves efficiency
• Increased number of outputs allows more independent multipliers
• Fractional mode with third-order delta-sigma modulation
• Integer mode
• Precision clock synthesis, clock delay compensation, and zero delay buffer
(ZDB)
• 800-MHz fabric clocking
• Global, quadrant, and peripheral clock networks
• Unused clock networks can be powered down to reduce dynamic power
Serial and parallel flash interface
Enhanced advanced encryption standard (AES) design security features
Tamper protection
Partial and dynamic reconfiguration
Configuration via Protocol (CvP)
Fractional PLLs
Clock networks
Device configuration
High-performance
packaging
• Multiple device densities with identical package footprints enables
seamless migration between different FPGA densities
• FBGA packaging with on-package decoupling capacitors
• Lead and RoHS-compliant lead-free options
HardCopy V migration
Stratix V Family Plan
The following tables list the features of the different Stratix V devices.
The information in this section is correct at the time of publication. For the latest information and to get
more details, refer to the Altera Product Selector.
Stratix V Device Overview
Send Feedback
Altera Corporation
4
Stratix V Family Plan
SV51001
2015.10.01
Table 2: Stratix V GT Device Features
Feature
5SGTC5
5SGTC7
Logic Elements (K)
ALMs
Registers (K)
28.05/12.5-Gbps Transceivers
PCIe hard IP Blocks
Fractional PLLs
M20K Memory Blocks
M20K Memory (MBits)
Variable Precision Multipliers (18x18)
Variable Precision Multipliers (27x27)
DDR3 SDRAM x72 DIMM Interfaces
425
160,400
642
4/32
1
28
2,304
45
512
256
4
622
234,720
939
4/32
1
28
2,560
50
512
256
4
User I/Os
(1)
, Full-Duplex LVDS, 28.05/12.5-Gbps Transceivers
Package
(2) (3)
5SGTC5
5SGTC7
KF40-F1517
(4)
(40 mm)
600, 150, 36
600, 150, 36
(1)
(2)
(3)
(4)
The number of GPIOs does not include transceiver I/Os. In the Quartus II software, the number of user I/
Os includes transceiver I/Os.
Packages are flipchip ball grid array (1.0-mm pitch).
Each package row offers pin migration (common board footprint) for all devices in the row.
Migration between select Stratix V GT devices and Stratix V GX devices is available. For more information,
refer to
Table 6
and to
AN 644: Migration Between Stratix V GX and Stratix V GT Devices.
Stratix V Device Overview
Send Feedback
Altera Corporation
SV51001
2015.10.01
Stratix V Family Plan
5
Table 3: Stratix V GX Device Features
Features
5SGXA
3
5SGXA
4
5SGXA
5
5SGXA
7
5SGXA
9
5SGXA
B
5SGXB
5
5SGXB
6
5SGXB
9
5SGXBB
Logic
Elements
(K)
ALMs
Registers
(K)
14.1-Gbps
Transceive
rs
PCIe hard
IP Blocks
Fractional
PLLs
M20K
Memory
Blocks
M20K
Memory
(MBits)
Variable
Precision
Multipliers
(18x18)
Variable
Precision
Multipliers
(27x27)
340
420
490
622
840
952
490
597
840
952
128,300 158,500 185,000 234,720 317,000 359,200 185,000 225,400 317,000
513
12, 24,
or 36
1 or 2
20
(5)
957
634
24 or
36
1 or 2
24
1,900
740
24, 36,
or 48
939
24, 36,
or 48
1,268
36 or
48
1,437
36 or
48
740
66
902
66
1,268
66
359,200
1,437
66
1, 2, or 1, 2, or 1, 2, or 1, 2, or
4
4
4
4
28
2,304
28
2,560
28
2,640
28
2,640
1 or 4
24
2,100
1 or 4
24
2,660
1 or 4
32
2,640
1 or 4
32
2,640
19
37
45
50
52
52
41
52
52
52
512
512
512
512
704
704
798
798
704
704
256
256
256
256
352
352
399
399
352
352
(5)
The F1517 package contains 24 PLLs. The other packages with this device contain 20 PLLs.
Altera Corporation
Stratix V Device Overview
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